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| kinetis k22f 512kb flash 120 mhz arm? cortex?-m4 based microcontroller with fpu the kinetis k22 product family members are optimized for cost- sensitive applications requiring low-power, usb connectivity, and processing efficiency and high peripheral integration with a floating point unit. these devices share the comprehensive enablement and scalability of the kinetis family. this product offers: ? run power consumption down to 156 a/mhz and static power consumption down to 3.8 a, full state retention and 6 s wakeup. lowest static mode down to 140 na. ? usb ls/fs otg 2.0 with embedded 3.3 v, 120 ma ldo voltage regulator. usb fs device crystal-less functionality. performance ? 120 mhz arm cortex-m4 core with dsp instructions delivering 1.25 dhrystone mips per mhz memories and memory interfaces ? 512 kb of embedded flash and 128 kb of ram ? flexbus external bus interface 1 ? serial programming interface (ezport) ? preprogrammed kinetis flashloader for one-time, in- system factory programming timers ? two 8-ch general purpose/pwm timers ? two 2-ch general purpose timers with quadrature decoder functionality ? periodic interrupt timers ? 16-bit low-power timer ? real-time clock with independent power domain ? programmable delay block security and integrity modules ? hardware crc module ? 128-bit unique identification (id) number per chip ? hardware random-number generator ? flash access control to protect proprietary software operating characteristics ? voltage range (including flash writes): 1.71 to 3.6 v ? temperature range (ambient): -40 to 105c analog modules ? two 16-bit sar adcs (1.2 ms/s in 12bit mode) ? two 12-bit dacs 2 ? two analog comparators (cmp) with 6-bit dac ? accurate internal voltage reference system peripherals ? flexible low-power modes, multiple wake-up sources ? 16-channel dma controller ? independent external and software watchdog monitor clocks ? two crystal oscillators: 32 khz (rtc) and 32-40 khz or 3-32 mhz ? three internal oscillators: 32 khz, 4 mhz, & 48 mhz ? multipurpose clock generator with pll and fll communication interfaces ? usb full/low-speed on-the-go controller ? usb full-speed device crystal-less operation ? two spi modules and i2s module ? three uart modules and one low-power uart ? two i2c: support for up to 1 mbps operation human-machine interface ? up to 81 general-purpose i/o (gpio) MK22FN512VDC12 mk22fn512vll12 mk22fn512vlh12 mk22fn512vmp12 mk22fn512vfx12 121 xfbga (dc) 8 x 8 x 0.5 mm p .65 100 & 64 lqfp(ll&lh) 14x14x1.4 mm p .5(ll) 10x10x1.4 mm p .5(lh) 64 mapbga (mp) 5 x 5 x 1.2 mm p .5 88 qfn (fx) 10 x 10 x 0.9 mm p .4 nxp semiconductors k22p121m120sf7 data sheet: technical data rev. 7.1, 08/2016 nxp reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.
1. mk22fn512vfx12 (88qfn) does not support the flexbus function. 2. mk22fn512vfx12 (88qfn) does not support the dac1 function. ordering information part number memory maximum number of i/o's flash (kb) sram (kb) MK22FN512VDC12 512 128 81 mk22fn512vll12 512 128 66 mk22fn512vlh12 512 128 40 mk22fn512vmp12 512 128 40 mk22fn512vfx12 512 128 60 device revision number device mask set number sim_sdid[revid] jtag id register[prn] 0n50m 0001 0001 related resources type description document selector guide the nxp solution advisor is a web-based tool that features interactive application wizards and a dynamic product selector kinetiskmcuselgd product brief the product brief contains concise overview/summary information to enable quick evaluation of a device for design suitability. k22fpb reference manual the reference manual contains a comprehensive description of the structure and function (operation) of a device. k22p121m120sf7rm data sheet the data sheet is this document. it includes electrical characteristics and signal connections. k22p121m120sf7 chip errata the chip mask set errata provides additional or corrective information for a particular device mask set. kinetis_k_ x n50m 1 package drawing package dimensions are provided by part number: ? MK22FN512VDC12 ? mk22fn512vll12 ? mk22fn512vlh12 ? mk22fn512vmp12 ? mk22fn512vfx12 package drawing: ? 98asa00595d ? 98ass23308w ? 98ass23234w ? 98asa00420d ? 98asa00935d engineering bulletin this engineering bulletin gives connection recommendations specifically for microcontrollers in dfn and qfn packages. electrical connection recommendations for the exposed pad on qfn and dfn packages. 1. to find the associated resource, go to nxp.com and perform a search using this term with the x replaced by the revision of the device you are using. figure 1 shows the functional modules in the chip. 2 kinetis k22f 512kb flash, rev. 7.1, 08/2016 nxp semiconductors memories and memory interfaces ram analog timers communication interfaces x1 clocks core dsp system dma (16ch) uart x3 ? cortex?-m4 arm fpu usb otg ls/fs i s 2 x 2 i c 2 flexbus spi x2 lpuart (128 kb) debug interfaces interrupt contoller low-leakage wakeup internal and external watchdogs program flash (512 kb) serial programming interface (ezport) phase- locked loop frequency- locked loop low/high frequency oscillators internal reference clocks 16-bit adc x2 comparator with 6-bit dac x2 12-bit dac x2 high performance voltage ref timers x2 (8ch) x2 (2ch) programmable delay block periodic interrupt timers 16-bit low-power timer independent real-time clock usb ls/fs transceiver usb voltage regulator up to 81 gpios human-machine interface (hmi) crc security and integrity flash access control random number generator figure 1. functional block diagram kinetis k22f 512kb flash, rev. 7.1, 08/2016 3 nxp semiconductors table of contents 1 ratings.................................................................................... 5 1.1 thermal handling ratings................................................. 5 1.2 moisture handling ratings................................................ 5 1.3 esd handling ratings....................................................... 5 1.4 voltage and current operating ratings............................. 5 2 general................................................................................... 6 2.1 ac electrical characteristics............................................. 6 2.2 nonswitching electrical specifications.............................. 6 2.2.1 voltage and current operating requirements....... 6 2.2.2 lvd and por operating requirements................ 7 2.2.3 voltage and current operating behaviors............. 8 2.2.4 power mode transition operating behaviors........ 9 2.2.5 power consumption operating behaviors............ 10 2.2.6 emc radiated emissions operating behaviors..... 17 2.2.7 designing with radiated emissions in mind.......... 18 2.2.8 capacitance attributes......................................... 18 2.3 switching specifications................................................... 18 2.3.1 device clock specifications.................................. 18 2.3.2 general switching specifications......................... 19 2.4 thermal specifications..................................................... 20 2.4.1 thermal operating requirements......................... 20 2.4.2 thermal attributes................................................ 20 2.4.3 thermal attributes for 88 qfn............................. 21 3 peripheral operating requirements and behaviors.................. 22 3.1 core modules.................................................................. 22 3.1.1 swd electricals .................................................. 22 3.1.2 jtag electricals.................................................. 23 3.2 system modules.............................................................. 26 3.3 clock modules................................................................. 26 3.3.1 mcg specifications.............................................. 26 3.3.2 irc48m specifications......................................... 29 3.3.3 oscillator electrical specifications........................ 29 3.3.4 32 khz oscillator electrical characteristics........... 32 3.4 memories and memory interfaces................................... 32 3.4.1 flash electrical specifications.............................. 32 3.4.2 ezport switching specifications........................... 34 3.4.3 flexbus switching specifications.......................... 35 3.5 security and integrity modules........................................ 38 3.6 analog............................................................................. 38 3.6.1 adc electrical specifications............................... 39 3.6.2 cmp and 6-bit dac electrical specifications....... 43 3.6.3 12-bit dac electrical characteristics.................... 45 3.6.4 voltage reference electrical specifications.......... 48 3.7 timers.............................................................................. 49 3.8 communication interfaces............................................... 49 3.8.1 usb electrical specifications............................... 50 3.8.2 usb vreg electrical specifications.................... 50 3.8.3 dspi switching specifications (limited voltage range).................................................................. 51 3.8.4 dspi switching specifications (full voltage range).................................................................. 53 3.8.5 inter-integrated circuit interface (i2c) timing...... 54 3.8.6 uart switching specifications............................ 56 3.8.7 i2s/sai switching specifications.......................... 56 4 dimensions............................................................................. 62 4.1 obtaining package dimensions....................................... 62 5 pinout...................................................................................... 63 5.1 k22f signal multiplexing and pin assignments.............. 63 5.2 recommended connection for unused analog and digital pins........................................................................ 69 5.3 k22 pinouts..................................................................... 70 6 part identification..................................................................... 75 6.1 description....................................................................... 75 6.2 format............................................................................. 75 6.3 fields............................................................................... 76 6.4 example........................................................................... 76 6.5 121-pin xfbga part marking.......................................... 77 6.6 64-pin mapbga part marking......................................... 77 7 terminology and guidelines.................................................... 77 7.1 definitions........................................................................ 77 7.2 examples......................................................................... 78 7.3 typical-value conditions.................................................. 78 7.4 relationship between ratings and operating requirements.................................................................... 79 7.5 guidelines for ratings and operating requirements.......... 79 8 revision history...................................................................... 79 4 kinetis k22f 512kb flash, rev. 7.1, 08/2016 nxp semiconductors 1 ratings 1.1 thermal handling ratings symbol description min. max. unit notes t stg storage temperature C55 150 c 1 t sdr solder temperature, lead-free 260 c 2 1. determined according to jedec standard jesd22-a103, high temperature storage life . 2. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . 1.2 moisture handling ratings symbol description min. max. unit notes msl moisture sensitivity level 3 1 1. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . 1.3 esd handling ratings symbol description min. max. unit notes v hbm electrostatic discharge voltage, human body model -2000 +2000 v 1 v cdm electrostatic discharge voltage, charged-device model -500 +500 v 2 i lat latch-up current at ambient temperature of 105c -100 +100 ma 3 1. determined according to jedec standard jesd22-a114, electrostatic discharge (esd) sensitivity testing human body model (hbm) . 2. determined according to jedec standard jesd22-c101, field-induced charged-device model test method for electrostatic-discharge-withstand thresholds of microelectronic components . 3. determined according to jedec standard jesd78, ic latch-up test . 1.4 voltage and current operating ratings ratings kinetis k22f 512kb flash, rev. 7.1, 08/2016 5 nxp semiconductors symbol description min. max. unit v dd digital supply voltage C0.3 3.8 v i dd digital supply current 169 ma v dio digital input voltage C0.3 v dd + 0.3 v v aio analog 1 C0.3 v dd + 0.3 v i d maximum current single pin limit (applies to all digital pins) C25 25 ma v dda analog supply voltage v dd C 0.3 v dd + 0.3 v v usb0_dp usb0_dp input voltage C0.3 3.63 v v usb0_dm usb0_dm input voltage C0.3 3.63 v vregin usb regulator input C0.3 6.0 v v bat rtc battery supply voltage C0.3 3.8 v 1. analog pins are defined as pins that do not have an associated general purpose i/o port function. 2 general 2.1 ac electrical characteristics unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. 80% 20% 50% v il input signal v ih fall time high low rise time midpoint1 the midpoint is v il + (v ih - v il ) / 2 figure 2. input signal measurement reference 2.2 nonswitching electrical specifications general 6 kinetis k22f 512kb flash, rev. 7.1, 08/2016 nxp semiconductors 2.2.1 voltage and current operating requirements table 1. voltage and current operating requirements symbol description min. max. unit notes v dd supply voltage 1.71 3.6 v v dda analog supply voltage 1.71 3.6 v v dd C v dda v dd -to-v dda differential voltage C0.1 0.1 v v ss C v ssa v ss -to-v ssa differential voltage C0.1 0.1 v v bat rtc battery supply voltage 1.71 3.6 v v ih input high voltage ? 2.7 v v dd 3.6 v ? 1.7 v v dd 2.7 v 0.7 v dd 0.75 v dd v v v il input low voltage ? 2.7 v v dd 3.6 v ? 1.7 v v dd 2.7 v 0.35 v dd 0.3 v dd v v v hys input hysteresis 0.06 v dd v i icio analog and i/o pin dc injection current single pin ? v in < v ss -0.3v (negative current injection) -3 ma 1 i iccont contiguous pin dc injection current regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins ? negative current injection -25 ma v odpu open drain pullup voltage level v dd v dd v 2 v ram v dd voltage required to retain ram 1.2 v v rfvbat v bat voltage required to retain the vbat register file v por_vbat v 1. all analog and i/o pins are internally clamped to v ss through esd protection diodes. if v in is less than v io_min or greater than v io_max , a current limiting resistor is required. the negative dc injection current limiting resistor is calculated as r=(v io_min -v in )/|i icio |. 2. open drain outputs must be pulled to vdd. 2.2.2 lvd and por operating requirements table 2. v dd supply lvd and por operating requirements symbol description min. typ. max. unit notes v por falling vdd por detect voltage 0.8 1.1 1.5 v v lvdh falling low-voltage detect threshold high range (lvdv=01) 2.48 2.56 2.64 v v lvw1h low-voltage warning thresholds high range ? level 1 falling (lvwv=00) 2.62 2.70 2.78 v 1 table continues on the next page... general kinetis k22f 512kb flash, rev. 7.1, 08/2016 7 nxp semiconductors table 2. v dd supply lvd and por operating requirements (continued) symbol description min. typ. max. unit notes v lvw2h v lvw3h v lvw4h ? level 2 falling (lvwv=01) ? level 3 falling (lvwv=10) ? level 4 falling (lvwv=11) 2.72 2.82 2.92 2.80 2.90 3.00 2.88 2.98 3.08 v v v v hysh low-voltage inhibit reset/recover hysteresis high range 80 mv v lvdl falling low-voltage detect threshold low range (lvdv=00) 1.54 1.60 1.66 v v lvw1l v lvw2l v lvw3l v lvw4l low-voltage warning thresholds low range ? level 1 falling (lvwv=00) ? level 2 falling (lvwv=01) ? level 3 falling (lvwv=10) ? level 4 falling (lvwv=11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 v v v v 1 v hysl low-voltage inhibit reset/recover hysteresis low range 60 mv v bg bandgap voltage reference 0.97 1.00 1.03 v t lpo internal low power oscillator period factory trimmed 900 1000 1100 s 1. rising threshold is the sum of falling threshold and hysteresis voltage table 3. vbat power operating requirements symbol description min. typ. max. unit notes v por_vbat falling vbat supply por detect voltage 0.8 1.1 1.5 v 2.2.3 voltage and current operating behaviors table 4. voltage and current operating behaviors symbol description min. typ. max. unit notes v oh output high voltage normal drive pad except reset_b 2.7 v v dd 3.6 v, i oh = -5 ma v dd C 0.5 v 1 1.71 v v dd 2.7 v, i oh = -2.5 ma v dd C 0.5 v v oh output high voltage high drive pad except reset_b 2.7 v v dd 3.6 v, i oh = -20 ma v dd C 0.5 v 1 1.71 v v dd 2.7 v, i oh = -10 ma v dd C 0.5 v i oht output high current total for all ports 100 ma table continues on the next page... general 8 kinetis k22f 512kb flash, rev. 7.1, 08/2016 nxp semiconductors table 4. voltage and current operating behaviors (continued) symbol description min. typ. max. unit notes v ol output low voltage normal drive pad except reset_b 2.7 v v dd 3.6 v, i ol = 5 ma 0.5 v 1 1.71 v v dd 2.7 v, i ol = 2.5 ma 0.5 v v ol output low voltage high drive pad except reset_b 2.7 v v dd 3.6 v, i ol = 20 ma 0.5 v 1 1.71 v v dd 2.7 v, i ol = 10 ma 0.5 v v ol output low voltage reset_b 2.7 v v dd 3.6 v, i ol = 3 ma 0.5 v 1.71 v v dd 2.7 v, i ol = 1.5 ma 0.5 v i olt output low current total for all ports 100 ma i in input leakage current (per pin) for full temperature range all pins other than high drive port pins 0.002 0.5 a 1 , 2 high drive port pins 0.004 0.5 a i in input leakage current (total all pins) for full temperature range 1.0 a 2 r pu internal pullup resistors 20 50 k 3 r pd internal pulldown resistors 20 50 k 4 1. ptb0, ptb1, ptc3, ptc4, ptd4, ptd5, ptd6, and ptd7 i/o have both high drive and normal drive capability selected by the associated ptx_pcrn[dse] control bit. all other gpios are normal drive only. 2. measured at vdd=3.6v 3. measured at v dd supply voltage = v dd min and vinput = v ss 4. measured at v dd supply voltage = v dd min and vinput = v dd 2.2.4 power mode transition operating behaviors all specifications except t por , and vllsx run recovery times in the following table assume this clock configuration: ? cpu and system clocks = 80 mhz ? bus clock = 40 mhz ? flexbus clock = 20 mhz ? flash clock = 20 mhz ? mcg mode: fei general kinetis k22f 512kb flash, rev. 7.1, 08/2016 9 nxp semiconductors table 5. power mode transition operating behaviors symbol description min. typ. max. unit notes t por after a por event, amount of time from the point v dd reaches 1.71 v to execution of the first instruction across the operating temperature range of the chip. 300 s 1 ? vlls0 run 140 s ? vlls1 run 140 s ? vlls2 run 80 s ? vlls3 run 80 s ? lls2 run 6 s ? lls3 run 6 s ? vlps run 5.7 s ? stop run 5.7 s 1. normal boot (ftfa_opt[lpboot]=1) 2.2.5 power consumption operating behaviors the current parameters in the table below are derived from code executing a while(1) loop from flash, unless otherwise noted. the idd typical values represent the statistical mean at 25c, and the idd maximum values for run, wait, vlpr, and vlpw represent data collected at 125c junction temperature unless otherwise noted. the maximum values represent characterized results equivalent to the mean plus three times the standard deviation (mean + 3 sigma). table 6. power consumption operating behaviors symbol description min. typ. max. unit notes i dda analog supply current see note ma 1 i dd_hsrun high speed run mode current - all peripheral clocks disabled, coremark benchmark code executing from flash table continues on the next page... general 10 kinetis k22f 512kb flash, rev. 7.1, 08/2016 nxp semiconductors table 6. power consumption operating behaviors (continued) symbol description min. typ. max. unit notes @ 1.8v 28.0 29.33 ma 2 , 3 , 4 @ 3.0v 28.0 29.33 ma i dd_hsrun high speed run mode current - all peripheral clocks disabled, code executing from flash @ 1.8v 25.6 26.93 ma 2 @ 3.0v 25.7 27.03 ma i dd_hsrun high speed run mode current all peripheral clocks enabled, code executing from flash @ 1.8v 35.5 36.83 ma 5 @ 3.0v 35.6 36.93 ma i dd_run run mode current in compute operation coremark benchmark code executing from flash @ 1.8v 17.5 18.83 ma 3 , 4 , 6 @ 3.0v 17.5 18.83 ma i dd_run run mode current in compute operation code executing from flash @ 1.8v 15.10 17.10 ma 6 @ 3.0v 15.10 17.33 ma i dd_run run mode current all peripheral clocks disabled, code executing from flash @ 1.8v 16.6 17.93 ma 7 @ 3.0v 16.8 18.13 ma i dd_run run mode current all peripheral clocks enabled, code executing from flash @ 1.8v 22.8 24.13 ma 8 @ 3.0v ? @ 25c 22.9 24.23 ma ? @ 70c 23.1 24.43 ma ? @ 85c 23.5 24.83 ma ? @ 105c 23.8 25.13 ma i dd_run run mode current compute operation, code executing from flash @ 1.8v 15.1 16.43 ma 9 @ 3.0v ? @ 25c 15.1 16.43 ma ? @ 70c 15.4 16.73 ma ? @ 85c 15.6 16.93 ma ? @ 105c 16.0 17.33 ma table continues on the next page... general kinetis k22f 512kb flash, rev. 7.1, 08/2016 11 nxp semiconductors table 6. power consumption operating behaviors (continued) symbol description min. typ. max. unit notes i dd_wait wait mode high frequency current at 3.0 v all peripheral clocks disabled 9.3 10.63 ma 7 i dd_wait wait mode reduced frequency current at 3.0 v all peripheral clocks disabled 5.4 6.73 ma 10 i dd_vlpr very-low-power run mode current in compute operation coremark benchmark code executing from flash @ 1.8v 0.88 1.02 ma 3 , 4 , 11 @ 3.0v 0.89 1.03 ma i dd_vlpr very-low-power run mode current in compute operation, code executing from flash @ 1.8v 0.62 0.77 ma 11 @ 3.0v 0.63 0.77 ma i dd_vlpr very-low-power run mode current at 3.0 v all peripheral clocks disabled 0.76 0.90 ma 12 i dd_vlpr very-low-power run mode current at 3.0 v all peripheral clocks enabled 1.2 1.34 ma 13 i dd_vlpw very-low-power wait mode current at 3.0 v all peripheral clocks disabled 0.45 0.59 ma 14 i dd_stop stop mode current at 3.0 v @ -40c to 25c 0.28 0.37 ma @ 70c 0.34 0.51 ma @ 85c 0.38 0.55 ma @ 105c 0.50 0.80 ma i dd_vlps very-low-power stop mode current at 3.0 v @ -40c to 25c 8.7 18.10 a @ 70c 31.1 79.55 a @ 85c 50.3 110.15 a @ 105c 98.6 238.30 a i dd_lls3 low leakage stop mode 3 current at 3.0 v @ -40c to 25c 3.8 5.65 a @ 70c 12.5 28.75 a @ 85c 20.2 47.60 a @ 105c 39.5 91.25 a i dd_lls2 low leakage stop mode 2 current at 3.0 v @ -40c to 25c 3.0 4.10 a @ 70c 7.8 16.40 a @ 85c 12.3 30.15 a @ 105c 23.6 55.30 a i dd_vlls3 very low-leakage stop mode 3 current at 3.0 v @ -40c to 25c 2.8 3.95 a table continues on the next page... general 12 kinetis k22f 512kb flash, rev. 7.1, 08/2016 nxp semiconductors table 6. power consumption operating behaviors (continued) symbol description min. typ. max. unit notes @ 70c 9.5 21.25 a @ 85c 15.3 34.65 a @ 105c 30.1 66.05 a i dd_vlls2 very low-leakage stop mode 2 current at 3.0 v @ -40c to 25c 1.9 2.45 a @ 70c 4.5 8.50 a @ 85c 6.8 12.15 a @ 105c 13.0 25.50 a i dd_vlls1 very low-leakage stop mode 1 current at 3.0 v @ -40c to 25c 0.73 1.42 a @ 70c 1.8 3.90 a @ 85c 3.0 5.25 a @ 105c 5.9 10.80 a i dd_vlls0 very low-leakage stop mode 0 current at 3.0 v with por detect circuit enabled @ -40c to 25c 0.43 0.55 a @ 70c 1.4 2.45 a @ 85c 2.6 4.00 a @ 105c 5.4 9.30 a i dd_vlls0 very low-leakage stop mode 0 current at 3.0 v with por detect circuit disabled @ -40c to 25c 0.14 0.24 a @ 70c 1.1 2.15 a @ 85c 2.3 3.85 a @ 105c 5.1 9.00 a i dd_vbat average current with rtc and 32khz disabled at 3.0 v @ -40c to 25c 0.18 0.21 a @ 70c 0.66 0.86 a @ 85c 1.52 2.24 a @ 105c 2.92 4.30 a i dd_vbat average current when cpu is not accessing rtc registers @ 1.8v ? @ -40c to 25c 0.59 0.70 a 15 ? @ 70c 1.00 1.3 a ? @ 85c 1.76 2.59 a ? @ 105c 3.00 4.42 a @ 3.0v table continues on the next page... general kinetis k22f 512kb flash, rev. 7.1, 08/2016 13 nxp semiconductors table 6. power consumption operating behaviors (continued) symbol description min. typ. max. unit notes ? @ -40c to 25c 0.71 0.84 a ? @ 70c 1.22 1.59 a ? @ 85c 2.08 3.06 a ? @ 105c 3.50 5.15 a 1. the analog supply current is the sum of the active or disabled current for each of the analog modules on the device. see each module's specification for its supply current. 2. 120mhz core and system clock, 60mhz bus clock, 24mhz flexbus clock, and 24mhz flash clock. mcg configured for pee mode. all peripheral clocks disabled. 3. cache on and prefetch on, low compiler optimization. 4. coremark benchmark compiled using iar 7.2 with optimization level low. 5. 120mhz core and system clock, 60mhz bus clock, 24mhz flexbus clock, and 24mhz flash clock. mcg configured for pee mode. all peripheral clocks enabled. 6. 80 mhz core and system clock, 40 mhz bus clock, and 26.67 mhz flash clock. mcg configured for pee mode. compute operation. 7. 80mhz core and system clock, 40mhz bus clock, 20mhz flexbus clock, and 26.67mhz flash clock. mcg configured for fei mode. all peripheral clocks disabled. 8. 80mhz core and system clock, 40mhz bus clock, 20mhz flexbus clock, and 26.67mhz flash clock. mcg configured for fei mode. all peripheral clocks enabled. 9. 80mhz core and system clock, 40mhz bus clock, and 26.67mhz flash clock. mcg configured for fei mode. compute operation. 10. 25mhz core and system clock, 25mhz bus clock, and 25mhz flexbus and flash clock. mcg configured for fei mode. 11. 4 mhz core, system, flexbus, and bus clock and 1mhz flash clock. mcg configured for blpe mode. compute operation. code executing from flash. 12. 4 mhz core, system, flexbus, and bus clock and 1mhz flash clock. mcg configured for blpe mode. all peripheral clocks disabled. code executing from flash. 13. 4 mhz core, system, flexbus, and bus clock and 1mhz flash clock. mcg configured for blpe mode. all peripheral clocks enabled but peripherals are not in active operation. code executing from flash. 14. 4 mhz core, system, flexbus, and bus clock and 1mhz flash clock. mcg configured for blpe mode. all peripheral clocks disabled. 15. includes 32khz oscillator current and rtc operation. table 7. low power mode peripheral adderstypical value symbol description temperature (c) unit -40 25 50 70 85 105 i irefsten4mhz 4 mhz internal reference clock (irc) adder. measured by entering stop or vlps mode with 4 mhz irc enabled. 56 56 56 56 56 56 a i irefsten32khz 32 khz internal reference clock (irc) adder. measured by entering stop mode with the 32 khz irc enabled. 52 52 52 52 52 52 a i erefsten4mhz external 4 mhz crystal clock adder. measured by entering stop or vlps mode with the crystal enabled. 206 228 237 245 251 258 ua i erefsten32khz external 32 khz crystal clock adder by means of the osc0_cr[erefsten table continues on the next page... general 14 kinetis k22f 512kb flash, rev. 7.1, 08/2016 nxp semiconductors table 7. low power mode peripheral adderstypical value (continued) symbol description temperature (c) unit -40 25 50 70 85 105 and erefsten] bits. measured by entering all modes with the crystal enabled. vlls1 vlls3 lls vlps stop 440 440 490 510 510 490 490 490 560 560 540 540 540 560 560 560 560 560 560 560 570 570 570 610 610 580 580 680 680 680 na i 48mirc 48 mhz internal reference clock 350 350 350 350 350 350 a i cmp cmp peripheral adder measured by placing the device in vlls1 mode with cmp enabled using the 6-bit dac and a single external input for compare. includes 6-bit dac power consumption. 22 22 22 22 22 22 a i rtc rtc peripheral adder measured by placing the device in vlls1 mode with external 32 khz crystal enabled by means of the rtc_cr[osce] bit and the rtc alarm set for 1 minute. includes erclk32k (32 khz external crystal) power consumption. 432 357 388 475 532 810 na i uart uart peripheral adder measured by placing the device in stop or vlps mode with selected clock source waiting for rx data at 115200 baud rate. includes selected clock source power consumption. mcgirclk (4 mhz internal reference clock) >oscerclk (4 mhz external crystal) 66 214 66 237 66 246 66 254 66 260 66 268 a i bg bandgap adder when bgen bit is set and device is placed in vlpx, lls, or vllsx mode. 45 45 45 45 45 45 a i adc adc peripheral adder combining the measured values at v dd and v dda by placing the device in stop or vlps mode. adc is configured for low power mode using the internal clock and continuous conversions. 42 42 42 42 42 42 a 2.2.5.1 diagram: typical idd_run operating behavior the following data was measured under these conditions: general kinetis k22f 512kb flash, rev. 7.1, 08/2016 15 nxp semiconductors ? mcg in fbe mode for 50 mhz and lower frequencies. mcg in fee mode at frequencies between 50 mhz and 100mhz. mcg in pee mode at frequencies greater than 100 mhz. ? usb regulator disabled ? no gpios toggled ? code execution from flash with cache enabled ? for the alloff curve, all peripheral clocks are disabled except ftfa run mode current vs core frequency temp (c)=25, vdd=3.6v, cache=enable, code residence=flash current consumption on vdd (a) clk ratio core-bus-flexbus-flash core freq (mhz) all peripheral clk gates alloff allon figure 3. run mode supply current vs. core frequency general 16 kinetis k22f 512kb flash, rev. 7.1, 08/2016 nxp semiconductors very low power run (vlpr) current vs core frequency temp (c)=25, vdd=3.6v, cache=enable, code residence=flash current consumption on vdd (a) clk ratio core-bus-flexbus-flash core freq (mhz) all peripheral clk gates alloff allon figure 4. vlpr mode supply current vs. core frequency 2.2.6 emc radiated emissions operating behaviors table 8. emc radiated emissions operating behaviors for 64 lqfp package parame ter conditions clocks frequency range level (typ.) unit notes v eme device configuration, test conditions and em testing per standard iec 61967-2. supply voltages: ? vregin (usb) = 5.0 v ? vdd = 3.3 v temp = 25c fsys = 120 mhz fbus = 60 mhz external crystal = 8 mhz 150 khzC50 mhz 14 dbuv 1 , 2 , 3 50 mhzC150 mhz 23 150 mhzC500 mhz 23 500 mhzC1000 mhz 9 iec level l 4 1. measurements were made per iec 61967-2 while the device was running typical application code. 2. measurements were performed on the 64lqfp device, mk22fn512vlh12 . general kinetis k22f 512kb flash, rev. 7.1, 08/2016 17 nxp semiconductors 3. the reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range. 4. iec level maximums: m 18dbmv, l 24dbmv, k 30dbmv, i 36dbmv, h 42dbmv . 2.2.7 designing with radiated emissions in mind to find application notes that provide guidance on designing your system to minimize interference from radiated emissions: ? go to nxp.com ? perform a keyword search for emc design. 2.2.8 capacitance attributes table 9. capacitance attributes symbol description min. max. unit c in_a input capacitance: analog pins 7 pf c in_d input capacitance: digital pins 7 pf 2.3 switching specifications 2.3.1 device clock specifications table 10. device clock specifications symbol description min. max. unit notes high speed run mode f sys system and core clock 120 mhz f bus bus clock 60 mhz normal run mode (and high speed run mode unless otherwise specified above) f sys system and core clock 80 mhz f sys_usb system and core clock when full speed usb in operation 20 mhz f bus bus clock 50 mhz fb_clk flexbus clock 30 mhz f flash flash clock 26.67 mhz f lptmr lptmr clock 25 mhz vlpr mode 1 table continues on the next page... general 18 kinetis k22f 512kb flash, rev. 7.1, 08/2016 nxp semiconductors table 10. device clock specifications (continued) symbol description min. max. unit notes f sys system and core clock 4 mhz f bus bus clock 4 mhz fb_clk flexbus clock 4 mhz f flash flash clock 1 mhz f erclk external reference clock 16 mhz f lptmr_pin lptmr clock 25 mhz f lptmr_erclk lptmr external reference clock 16 mhz f i2s_mclk i2s master clock 12.5 mhz f i2s_bclk i2s bit clock 4 mhz 1. the frequency limitations in vlpr mode here override any frequency specification listed in the timing specification for any other module. 2.3.2 general switching specifications these general purpose specifications apply to all signals configured for gpio, uart, and timers. table 11. general switching specifications symbol description min. max. unit notes gpio pin interrupt pulse width (digital glitch filter disabled) synchronous path 1.5 bus clock cycles 1 , 2 external reset and nmi pin interrupt pulse width asynchronous path 100 ns 3 gpio pin interrupt pulse width (digital glitch filter disabled, passive filter disabled) asynchronous path 50 ns 4 mode select ( ezp_cs) hold time after reset deassertion 2 bus clock cycles port rise and fall time ? slew disabled ? 1.71 v dd 2.7v ? 2.7 v dd 3.6v ? slew enabled ? 1.71 v dd 2.7v ? 2.7 v dd 3.6v 10 5 30 16 ns ns ns ns 5 1. this is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. shorter pulses may or may not be recognized. in stop, vlps, lls, and vllsx modes, the synchronizer is bypassed so shorter pulses can be recognized in that case. general kinetis k22f 512kb flash, rev. 7.1, 08/2016 19 nxp semiconductors 2. the greater of synchronous and asynchronous timing must be met. 3. these pins have a passive filter enabled on the inputs. this is the shortest pulse width that is guaranteed to be recognized. 4. these pins do not have a passive filter on the inputs. this is the shortest pulse width that is guaranteed to be recognized. 5. 25 pf load 2.4 thermal specifications 2.4.1 thermal operating requirements table 12. thermal operating requirements symbol description min. max. unit notes t j die junction temperature C40 125 c t a ambient temperature C40 105 c 1 1. maximum t a can be exceeded only if the user ensures that t j does not exceed maximum t j . the simplest method to determine t j is: t j = t a + r ja chip power dissipation. 2.4.2 thermal attributes board type symbol description 121 xfbga 100 lqfp 64 lqfp 64 mapb ga unit notes single- layer (1s) r ja thermal resistance, junction to ambient (natural convection) 44.4 61 67 95.7 c/w 1 four-layer (2s2p) r ja thermal resistance, junction to ambient (natural convection) 27.0 48 48 48.8 c/w 2 single- layer (1s) r jma thermal resistance, junction to ambient (200 ft./min. air speed) 37.2 51 55 74.4 c/w 3 four-layer (2s2p) r jma thermal resistance, junction to ambient (200 ft./min. air speed) 23.7 42 42 44.0 c/w 3 r jb thermal resistance, junction to board 23.5 34 31 30.3 c/w 4 r jc thermal resistance, junction to case 17.4 16 16 28.0 c/w 5 jt thermal characterization parameter, junction to package top outside 0.2 3 3 1.0 c/w 6 general 20 kinetis k22f 512kb flash, rev. 7.1, 08/2016 nxp semiconductors board type symbol description 121 xfbga 100 lqfp 64 lqfp 64 mapb ga unit notes center (natural convection) 1. determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditionsnatural convection (still air) with the single layer board horizontal. board meets jesd51-9 specification. 2. determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditionsnatural convection (still air). 3. determined according to jedec standard jesd51-6, integrated circuits thermal test method environmental conditionsforced convection (moving air) with the board horizontal. 4. determined according to jedec standard jesd51-8, integrated circuit thermal test method environmental conditionsjunction-to-board . 5. thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1). 6. thermal characterization parameter indicating the temperature difference between package top and the junction temperature per jedec jesd51-2. 2.4.3 thermal attributes for 88 qfn board type symbol description 88 qfn unit notes single-layer (1s) r ja thermal resistance, junction to ambient (natural convection) 55 c/w 1 , 2 four-layer (2s2p) r ja thermal resistance, junction to ambient (natural convection) 20 c/w 1 , 2 single-layer (1s) r jma thermal resistance, junction to ambient (200 ft./ min. air speed) 50 c/w 1 , 3 four-layer (2s2p) r jma thermal resistance, junction to ambient (200 ft./ min. air speed) 15 c/w 1 , 3 r jb thermal resistance, junction to board 7 c/w 4 r jc thermal resistance, junction to case 1 c/w 5 jt thermal characterization 1 c/w 6 general kinetis k22f 512kb flash, rev. 7.1, 08/2016 21 nxp semiconductors board type symbol description 88 qfn unit notes parameter, junction to package top outside center (natural convection) 1. junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. per jedec jesd51-2 with natural convection for horizontally oriented board. board meets jesd51-9 specification for 1s or 2s2p board, respectively. 3. per jedec jesd51-6 with forced convection for horizontally oriented board. board meets jesd51-9 specification for 1s or 2s2p board, respectively. 4. thermal resistance between the die and the printed circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 5. thermal resistance between the die and the solder pad on the bottom of the package. interface resistance is ignored. 6. thermal characterization parameter indicating the temperature difference between package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the thermal characterization parameter is written as psi-jt. 3 peripheral operating requirements and behaviors 3.1 core modules 3.1.1 swd electricals table 13. swd full voltage range electricals symbol description min. max. unit operating voltage 1.71 3.6 v s1 swd_clk frequency of operation ? serial wire debug 0 33 mhz s2 swd_clk cycle period 1/s1 ns s3 swd_clk clock pulse width ? serial wire debug 15 ns s4 swd_clk rise and fall times 3 ns s9 swd_dio input data setup time to swd_clk rise 8 ns s10 swd_dio input data hold time after swd_clk rise 1.4 ns s11 swd_clk high to swd_dio data valid 25 ns s12 swd_clk high to swd_dio high-z 5 ns peripheral operating requirements and behaviors 22 kinetis k22f 512kb flash, rev. 7.1, 08/2016 nxp semiconductors s2 s3 s3 s4 s4 swd_clk (input) figure 5. serial wire clock input timing s11 s12 s11 s9 s10 input data valid output data valid output data valid swd_clk swd_dio swd_dio swd_dio swd_dio figure 6. serial wire data timing 3.1.2 jtag electricals table 14. jtag limited voltage range electricals symbol description min. max. unit operating voltage 2.7 3.6 v j1 tclk frequency of operation ? boundary scan ? jtag and cjtag 0 0 10 20 mhz j2 tclk cycle period 1/j1 ns j3 tclk clock pulse width 50 ns table continues on the next page... peripheral operating requirements and behaviors kinetis k22f 512kb flash, rev. 7.1, 08/2016 23 nxp semiconductors table 14. jtag limited voltage range electricals (continued) symbol description min. max. unit ? boundary scan ? jtag and cjtag 25 ns j4 tclk rise and fall times 3 ns j5 boundary scan input data setup time to tclk rise 20 ns j6 boundary scan input data hold time after tclk rise 1 ns j7 tclk low to boundary scan output data valid 25 ns j8 tclk low to boundary scan output high-z 25 ns j9 tms, tdi input data setup time to tclk rise 8 ns j10 tms, tdi input data hold time after tclk rise 1 ns j11 tclk low to tdo data valid 19 ns j12 tclk low to tdo high-z 19 ns j13 trst assert time 100 ns j14 trst setup time (negation) to tclk high 8 ns table 15. jtag full voltage range electricals symbol description min. max. unit operating voltage 1.71 3.6 v j1 tclk frequency of operation ? boundary scan ? jtag and cjtag 0 0 10 15 mhz j2 tclk cycle period 1/j1 ns j3 tclk clock pulse width ? boundary scan ? jtag and cjtag 50 33 ns ns j4 tclk rise and fall times 3 ns j5 boundary scan input data setup time to tclk rise 20 ns j6 boundary scan input data hold time after tclk rise 1.4 ns j7 tclk low to boundary scan output data valid 27 ns j8 tclk low to boundary scan output high-z 27 ns j9 tms, tdi input data setup time to tclk rise 8 ns j10 tms, tdi input data hold time after tclk rise 1.4 ns j11 tclk low to tdo data valid 26.2 ns j12 tclk low to tdo high-z 26.2 ns j13 trst assert time 100 ns j14 trst setup time (negation) to tclk high 8 ns peripheral operating requirements and behaviors 24 kinetis k22f 512kb flash, rev. 7.1, 08/2016 nxp semiconductors j2 j3 j3 j4 j4 tclk (input) figure 7. test clock input timing j7 j8 j7 j5 j6 input data valid output data valid output data valid tclk data inputs data outputs data outputs data outputs figure 8. boundary scan (jtag) timing peripheral operating requirements and behaviors kinetis k22f 512kb flash, rev. 7.1, 08/2016 25 nxp semiconductors j11 j12 j11 j9 j10 input data valid output data valid output data valid tclk tdi/tms tdo tdo tdo figure 9. test access port timing j14 j13 tclk trst figure 10. trst timing 3.2 system modules there are no specifications necessary for the device's system modules. 3.3 clock modules peripheral operating requirements and behaviors 26 kinetis k22f 512kb flash, rev. 7.1, 08/2016 nxp semiconductors 3.3.1 mcg specifications table 16. mcg specifications symbol description min. typ. max. unit notes f ints_ft internal reference frequency (slow clock) factory trimmed at nominal vdd and 25 c 32.768 khz f ints_t total deviation of internal reference frequency (slow clock) over voltage and temperature +0.5/-0.7 2 % f ints_t internal reference frequency (slow clock) user trimmed 31.25 39.0625 khz fdco_res_t resolution of trimmed average dco output frequency at fixed voltage and temperature using sctrim and scftrim 0.3 0.6 %f dco 1 f dco_t total deviation of trimmed average dco output frequency over voltage and temperature +0.5/-0.7 2 %f dco 1 , 2 f dco_t total deviation of trimmed average dco output frequency over fixed voltage and temperature range of 0C70c 0.3 1.5 %f dco 1 f intf_ft internal reference frequency (fast clock) factory trimmed at nominal vdd and 25c 4 mhz f intf_ft frequency deviation of internal reference clock (fast clock) over temperature and voltage factory trimmed at nominal vdd and 25 c +1/-2 5 %f intf_ft f intf_t internal reference frequency (fast clock) user trimmed at nominal vdd and 25 c 3 5 mhz f loc_low loss of external clock minimum frequency range = 00 (3/5) x f ints_t khz f loc_high loss of external clock minimum frequency range = 01, 10, or 11 (16/5) x f ints_t khz fll f fll_ref fll reference frequency range 31.25 39.0625 khz f dco dco output frequency range low range (drs=00) 640 f fll_ref 20 20.97 25 mhz 3 , 4 mid range (drs=01) 1280 f fll_ref 40 41.94 50 mhz mid-high range (drs=10) 1920 f fll_ref 60 62.91 75 mhz high range (drs=11) 2560 f fll_ref 80 83.89 100 mhz f dco_t_dmx3 2 dco output frequency low range (drs=00) 732 f fll_ref 23.99 mhz 5 , 6 mid range (drs=01) 1464 f fll_ref 47.97 mhz mid-high range (drs=10) 71.99 mhz table continues on the next page... peripheral operating requirements and behaviors kinetis k22f 512kb flash, rev. 7.1, 08/2016 27 nxp semiconductors table 16. mcg specifications (continued) symbol description min. typ. max. unit notes 2197 f fll_ref high range (drs=11) 2929 f fll_ref 95.98 mhz j cyc_fll fll period jitter ? f vco = 48 mhz ? f vco = 98 mhz 180 150 ps t fll_acquire fll target frequency acquisition time 1 ms 7 pll f vco vco operating frequency 48.0 120 mhz i pll pll operating current ? pll @ 96 mhz (f osc_hi_1 = 8 mhz, f pll_ref = 2 mhz, vdiv multiplier = 48) 1060 a 8 i pll pll operating current ? pll @ 48 mhz (f osc_hi_1 = 8 mhz, f pll_ref = 2 mhz, vdiv multiplier = 24) 600 a 8 f pll_ref pll reference frequency range 2.0 4.0 mhz j cyc_pll pll period jitter (rms) ? f vco = 48 mhz ? f vco = 100 mhz 120 75 ps ps 9 j acc_pll pll accumulated jitter over 1s (rms) ? f vco = 48 mhz ? f vco = 100 mhz 1350 600 ps ps 9 d lock lock entry frequency tolerance 1.49 2.98 % d unl lock exit frequency tolerance 4.47 5.97 % t pll_lock lock detector detection time 150 10 -6 + 1075(1/ f pll_ref ) s 10 1. this parameter is measured with the internal reference (slow clock) being used as a reference to the fll (fei clock mode). 2. 2.0 v <= vdd <= 3.6 v. 3. these typical values listed are with the slow internal reference clock (fei) using factory trim and dmx32=0. 4. the resulting system clock frequencies should not exceed their maximum specified values. the dco frequency deviation ( f dco_t ) over voltage and temperature should be considered. 5. these typical values listed are with the slow internal reference clock (fei) using factory trim and dmx32=1. 6. the resulting clock frequency must not exceed the maximum specified clock frequency of the device. 7. this specification applies to any time the fll reference source or reference divider is changed, trim value is changed, dmx32 bit is changed, drs bits are changed, or changing from fll disabled (blpe, blpi) to fll enabled (fei, fee, fbe, fbi). if a crystal/resonator is being used as the reference, this specification assumes it is already running. 8. excludes any oscillator currents that are also consuming power while pll is in operation. 9. this specification was obtained using a nxp developed pcb. pll jitter is dependent on the noise characteristics of each pcb and results will vary. 10. this specification applies to any time the pll vco divider or reference divider is changed, or changing from pll disabled (blpe, blpi) to pll enabled (pbe, pee). if a crystal/resonator is being used as the reference, this specification assumes it is already running. peripheral operating requirements and behaviors 28 kinetis k22f 512kb flash, rev. 7.1, 08/2016 nxp semiconductors 3.3.2 irc48m specifications table 17. irc48m specifications symbol description min. typ. max. unit notes v dd supply voltage 1.71 3.6 v i dd48m supply current 400 500 a f irc48m internal reference frequency 48 mhz f irc48m_ol_hv open loop total deviation of irc48m frequency at high voltage (vdd=1.89v-3.6v) over 0c to 70c regulator enable (usb_clk_recover_irc_en[reg_en]=1) 0.2 0.5 %f irc48m 1 f irc48m_ol_hv open loop total deviation of irc48m frequency at high voltage (vdd=1.89v-3.6v) over full temperature regulator enable (usb_clk_recover_irc_en[reg_en]=1) 0.4 1.0 %f irc48m 1 f irc48m_ol_lv open loop total deviation of irc48m frequency at low voltage (vdd=1.71v-1.89v) over full temperature 1 regulator disable (usb_clk_recover_irc_en[reg_en]=0) 0.4 1.0 %f irc48m regulator enable (usb_clk_recover_irc_en[reg_en]=1) 0.5 1.5 f irc48m_cl closed loop total deviation of irc48m frequency over voltage and temperature 0.1 %f host 2 j cyc_irc48m period jitter (rms) 35 150 ps t irc48mst startup time 2 3 s 3 1. the maximum value represents characterized results equivalent to the mean plus or minus three times the standard deviation (mean 3 sigma). 2. closed loop operation of the irc48m is only feasible for usb device operation; it is not usable for usb host operation. it is enabled by configuring for usb device, selecting irc48m as usb clock source, and enabling the clock recover function (usb_clk_recover_irc_ctrl[clock_recover_en]=1, usb_clk_recover_irc_en[irc_en]=1). 3. irc48m startup time is defined as the time between clock enablement and clock availability for system use. enable the clock by one of the following settings: ? usb_clk_recover_irc_en[irc_en]=1 or ? mcg operating in an external clocking mode and mcg_c7[oscsel]=10 or mcg_c5[pllclken0]=1, or ? sim_sopt2[pllfllsel]=11 3.3.3 oscillator electrical specifications peripheral operating requirements and behaviors kinetis k22f 512kb flash, rev. 7.1, 08/2016 29 nxp semiconductors 3.3.3.1 oscillator dc electrical specifications table 18. oscillator dc electrical specifications symbol description min. typ. max. unit notes v dd supply voltage 1.71 3.6 v i ddosc supply current low-power mode (hgo=0) ? 32 khz ? 4 mhz ? 8 mhz (range=01) ? 16 mhz ? 24 mhz ? 32 mhz 500 200 300 950 1.2 1.5 na a a a ma ma 1 i ddosc supply current high-gain mode (hgo=1) ? 32 khz ? 4 mhz ? 8 mhz (range=01) ? 16 mhz ? 24 mhz ? 32 mhz 25 400 500 2.5 3 4 a a a ma ma ma 1 c x extal load capacitance 2 , 3 c y xtal load capacitance 2 , 3 r f feedback resistor low-frequency, low-power mode (hgo=0) m 2 , 4 feedback resistor low-frequency, high-gain mode (hgo=1) 10 m feedback resistor high-frequency, low-power mode (hgo=0) m feedback resistor high-frequency, high-gain mode (hgo=1) 1 m r s series resistor low-frequency, low-power mode (hgo=0) k series resistor low-frequency, high-gain mode (hgo=1) 200 k series resistor high-frequency, low-power mode (hgo=0) k series resistor high-frequency, high-gain mode (hgo=1) 0 k v pp 5 peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, low-power mode (hgo=0) 0.6 v table continues on the next page... peripheral operating requirements and behaviors 30 kinetis k22f 512kb flash, rev. 7.1, 08/2016 nxp semiconductors table 18. oscillator dc electrical specifications (continued) symbol description min. typ. max. unit notes peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, high-gain mode (hgo=1) v dd v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, low-power mode (hgo=0) 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, high-gain mode (hgo=1) v dd v 1. v dd =3.3 v, temperature =25 c 2. see crystal or resonator manufacturer's recommendation 3. c x and c y can be provided by using either integrated capacitors or external components. 4. when low-power mode is selected, r f is integrated and must not be attached externally. 5. the extal and xtal pins should only be connected to required oscillator components and must not be connected to any other device. 3.3.3.2 oscillator frequency specifications table 19. oscillator frequency specifications symbol description min. typ. max. unit notes f osc_lo oscillator crystal or resonator frequency low- frequency mode (mcg_c2[range]=00) 32 40 khz f osc_hi_1 oscillator crystal or resonator frequency high-frequency mode (low range) (mcg_c2[range]=01) 3 8 mhz f osc_hi_2 oscillator crystal or resonator frequency high frequency mode (high range) (mcg_c2[range]=1x) 8 32 mhz f ec_extal input clock frequency (external clock mode) 50 mhz 1 , 2 t dc_extal input clock duty cycle (external clock mode) 40 50 60 % t cst crystal startup time 32 khz low-frequency, low-power mode (hgo=0) 750 ms 3 , 4 crystal startup time 32 khz low-frequency, high-gain mode (hgo=1) 250 ms crystal startup time 8 mhz high-frequency (mcg_c2[range]=01), low-power mode (hgo=0) 0.6 ms crystal startup time 8 mhz high-frequency (mcg_c2[range]=01), high-gain mode (hgo=1) 1 ms 1. other frequency limits may apply when external clock is being used as a reference for the fll or pll. 2. when transitioning from fei or fbi to fbe mode, restrict the frequency of the input clock so that, when it is divided by frdiv, it remains within the limits of the dco input clock frequency. 3. proper pc board layout procedures must be followed to achieve specifications. peripheral operating requirements and behaviors kinetis k22f 512kb flash, rev. 7.1, 08/2016 31 nxp semiconductors 4. crystal startup time is defined as the time between the oscillator being enabled and the oscinit bit in the mcg_s register being set. 3.3.4 32 khz oscillator electrical characteristics 3.3.4.1 32 khz oscillator dc electrical specifications table 20. 32khz oscillator dc electrical specifications symbol description min. typ. max. unit v bat supply voltage 1.71 3.6 v r f internal feedback resistor 100 m c para parasitical capacitance of extal32 and xtal32 5 7 pf v pp 1 peak-to-peak amplitude of oscillation 0.6 v 1. when a crystal is being used with the 32 khz oscillator, the extal32 and xtal32 pins should only be connected to required oscillator components and must not be connected to any other devices. 3.3.4.2 32 khz oscillator frequency specifications table 21. 32 khz oscillator frequency specifications symbol description min. typ. max. unit notes f osc_lo oscillator crystal 32.768 khz t start crystal start-up time 1000 ms 1 f ec_extal32 externally provided input clock frequency 32.768 khz 2 v ec_extal32 externally provided input clock amplitude 700 v bat mv 2 , 3 1. proper pc board layout procedures must be followed to achieve specifications. 2. this specification is for an externally supplied clock driven to extal32 and does not apply to any other clock input. the oscillator remains enabled and xtal32 must be left unconnected. 3. the parameter specified is a peak-to-peak value and v ih and v il specifications do not apply. the voltage of the applied clock must be within the range of v ss to v bat . 3.4 memories and memory interfaces 3.4.1 flash electrical specifications this section describes the electrical characteristics of the flash memory module. peripheral operating requirements and behaviors 32 kinetis k22f 512kb flash, rev. 7.1, 08/2016 nxp semiconductors 3.4.1.1 flash timing specifications program and erase the following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. table 22. nvm program/erase timing specifications symbol description min. typ. max. unit notes t hvpgm4 longword program high-voltage time 7.5 18 s t hversscr sector erase high-voltage time 13 113 ms 1 t hversblk256k erase block high-voltage time for 256 kb 104 904 ms 1 1. maximum time based on expectations at cycling end-of-life. 3.4.1.2 flash timing specifications commands table 23. flash command timing specifications symbol description min. typ. max. unit notes t rd1blk256k read 1s block execution time ? 256 kb program flash 1.7 ms 1 t rd1sec2k read 1s section execution time (flash sector) 60 s 1 t pgmchk program check execution time 45 s 1 t rdrsrc read resource execution time 30 s 1 t pgm4 program longword execution time 65 145 s t ersblk256k erase flash block execution time ? 256 kb program flash 250 1500 ms 2 t ersscr erase flash sector execution time 14 114 ms 2 t rd1all read 1s all blocks execution time 1.8 ms 1 t rdonce read once execution time 30 s 1 t pgmonce program once execution time 100 s t ersall erase all blocks execution time 500 3000 ms 2 t vfykey verify backdoor access key execution time 30 s 1 1. assumes 25 mhz flash clock frequency. 2. maximum times for erase parameters based on expectations at cycling end-of-life. 3.4.1.3 flash high voltage current behaviors table 24. flash high voltage current behaviors symbol description min. typ. max. unit i dd_pgm average current adder during high voltage flash programming operation 2.5 6.0 ma table continues on the next page... peripheral operating requirements and behaviors kinetis k22f 512kb flash, rev. 7.1, 08/2016 33 nxp semiconductors table 24. flash high voltage current behaviors (continued) symbol description min. typ. max. unit i dd_ers average current adder during high voltage flash erase operation 1.5 4.0 ma 3.4.1.4 reliability specifications table 25. nvm reliability specifications symbol description min. typ. 1 max. unit notes program flash t nvmretp10k data retention after up to 10 k cycles 5 50 years t nvmretp1k data retention after up to 1 k cycles 20 100 years n nvmcycp cycling endurance 10 k 50 k cycles 2 1. typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25 c use profile. engineering bulletin eb618 does not apply to this technology. typical endurance defined in engineering bulletin eb619. 2. cycling endurance represents number of program/erase cycles at C40 c t j 125 c. 3.4.2 ezport switching specifications table 26. ezport switching specifications num description min. max. unit operating voltage 1.71 3.6 v ep1 ezp_ck frequency of operation (all commands except read) f sys /2 mhz ep1a ezp_ck frequency of operation (read command) f sys /8 mhz ep2 ezp_cs negation to next ezp_cs assertion 2 x t ezp_ck ns ep3 ezp_cs input valid to ezp_ck high (setup) 5 ns ep4 ezp_ck high to ezp_cs input invalid (hold) 5 ns ep5 ezp_d input valid to ezp_ck high (setup) 2 ns ep6 ezp_ck high to ezp_d input invalid (hold) 5 ns ep7 ezp_ck low to ezp_q output valid 25 ns ep8 ezp_ck low to ezp_q output invalid (hold) 0 ns ep9 ezp_cs negation to ezp_q tri-state 12 ns peripheral operating requirements and behaviors 34 kinetis k22f 512kb flash, rev. 7.1, 08/2016 nxp semiconductors ep2 ep3 ep4 ep5 ep6 ep7 ep8 ep9 ezp_ck ezp_cs ezp_q (output) ezp_d (input) figure 11. ezport timing diagram 3.4.3 flexbus switching specifications all processor bus timings are synchronous; input setup/hold and output delay are given in respect to the rising edge of a reference clock, fb_clk. the fb_clk frequency may be the same as the internal system bus frequency or an integer divider of that frequency. the following timing numbers indicate when data is latched or driven onto the external bus, relative to the flexbus output clock (fb_clk). all other timing relationships can be derived from these values. table 27. flexbus limited voltage range switching specifications num description min. max. unit notes operating voltage 2.7 3.6 v frequency of operation 30 mhz fb1 clock period 33.3 ns fb2 address, data, and control output valid 15 ns fb3 address, data, and control output hold 0.5 ns 1 fb4 data and fb_ta input setup 14.5 ns fb5 data and fb_ta input hold 0.5 ns 2 1. specification is valid for all fb_ad[31:0], fb_be/bwe n , fb_cs n , fb_oe, fb_r/ w, fb_tbst, fb_tsiz[1:0], fb_ale, and fb_ts. peripheral operating requirements and behaviors kinetis k22f 512kb flash, rev. 7.1, 08/2016 35 nxp semiconductors 2. specification is valid for all fb_ad[31:0] and fb_ta. table 28. flexbus full voltage range switching specifications num description min. max. unit notes operating voltage 1.71 3.6 v frequency of operation 30 mhz fb1 clock period 33.3 ns fb2 address, data, and control output valid 21.5 ns fb3 address, data, and control output hold C1.0 ns 1 fb4 data and fb_ta input setup 20.0 ns fb5 data and fb_ta input hold 0.5 ns 2 1. specification is valid for all fb_ad[31:0], fb_be/bwe n , fb_cs n , fb_oe, fb_r/ w, fb_tbst, fb_tsiz[1:0], fb_ale, and fb_ts. 2. specification is valid for all fb_ad[31:0] and fb_ta. peripheral operating requirements and behaviors 36 kinetis k22f 512kb flash, rev. 7.1, 08/2016 nxp semiconductors address address data tsiz aa=1 aa=0 aa=1 aa=0 fb3 fb5 fb4 fb4 fb5 fb1 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_ben fb_ta fb_tsiz[1:0] fb2 read timing parameters electricals_read.svg s0 s1 s2 s3 s0 s0 s1 s2 s3 s0 figure 12. flexbus read timing diagram peripheral operating requirements and behaviors kinetis k22f 512kb flash, rev. 7.1, 08/2016 37 nxp semiconductors address address data tsiz aa=1 aa=0 aa=1 aa=0 fb1 fb3 fb4 fb5 fb2 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_ben fb_ta fb_tsiz[1:0] write timing parameters electricals_write.svg figure 13. flexbus write timing diagram 3.5 security and integrity modules there are no specifications necessary for the device's security and integrity modules. 3.6 analog peripheral operating requirements and behaviors 38 kinetis k22f 512kb flash, rev. 7.1, 08/2016 nxp semiconductors 3.6.1 adc electrical specifications the 16-bit accuracy specifications listed in table 29 and table 30 are achievable on the differential pins adcx_dpx, adcx_dmx. all other adc channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 3.6.1.1 16-bit adc operating conditions table 29. 16-bit adc operating conditions symbol description conditions min. typ. 1 max. unit notes v dda supply voltage absolute 1.71 3.6 v v dda supply voltage delta to v dd (v dd C v dda ) -100 0 +100 mv 2 v ssa ground voltage delta to v ss (v ss C v ssa ) -100 0 +100 mv 2 v refh adc reference voltage high 1.13 v dda v dda v v refl adc reference voltage low v ssa v ssa v ssa v v adin input voltage ? 16-bit differential mode ? all other modes vrefl vrefl 31/32 * vrefh vrefh v c adin input capacitance ? 16-bit mode ? 8-bit / 10-bit / 12-bit modes 8 4 10 5 pf r adin input series resistance 2 5 k r as analog source resistance (external) 13-bit / 12-bit modes f adck < 4 mhz 5 k 3 f adck adc conversion clock frequency 13-bit mode 1.0 24.0 mhz 4 f adck adc conversion clock frequency 16-bit mode 2.0 12.0 mhz 4 c rate adc conversion rate 13-bit modes no adc hardware averaging continuous conversions enabled, subsequent conversion time 20 1200 ksps 5 c rate adc conversion rate 16-bit mode no adc hardware averaging 37 461 ksps 5 peripheral operating requirements and behaviors kinetis k22f 512kb flash, rev. 7.1, 08/2016 39 nxp semiconductors table 29. 16-bit adc operating conditions symbol description conditions min. typ. 1 max. unit notes continuous conversions enabled, subsequent conversion time 1. typical values assume v dda = 3.0 v, temp = 25 c, f adck = 1.0 mhz, unless otherwise stated. typical values are for reference only, and are not tested in production. 2. dc potential difference. 3. this resistance is external to mcu. to achieve the best results, the analog source resistance must be kept as low as possible. the results in this data sheet were derived from a system that had < 8 analog source resistance. the r as /c as time constant should be kept to < 1 ns. 4. to use the maximum adc conversion clock frequency, cfg2[adhsc] must be set and cfg1[adlpc] must be clear. 5. for guidelines and examples of conversion rate calculation, download the adc calculator tool . r as v as c as z as v adin z adin r adin r adin r adin r adin c adin pad leakage due to input protection input pin input pin input pin simplified input pin equivalent circuit simplified channel select circuit adc sar engine figure 14. adc input impedance equivalency diagram 3.6.1.2 16-bit adc electrical characteristics table 30. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) symbol description conditions 1 min. typ. 2 max. unit notes i dda_adc supply current 0.215 1.7 ma 3 table continues on the next page... peripheral operating requirements and behaviors 40 kinetis k22f 512kb flash, rev. 7.1, 08/2016 nxp semiconductors table 30. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) (continued) symbol description conditions 1 min. typ. 2 max. unit notes f adack adc asynchronous clock source ? adlpc = 1, adhsc = 0 ? adlpc = 1, adhsc = 1 ? adlpc = 0, adhsc = 0 ? adlpc = 0, adhsc = 1 1.2 2.4 3.0 4.4 2.4 4.0 5.2 6.2 3.9 6.1 7.3 9.5 mhz mhz mhz mhz t adack = 1/ f adack sample time see reference manual chapter for sample times tue total unadjusted error ? 12-bit modes ? <12-bit modes 4 1.4 6.8 2.1 lsb 4 5 dnl differential non- linearity ? 12-bit modes ? <12-bit modes 0.7 0.2 C1.1 to +1.9 C0.3 to 0.5 lsb 4 5 inl integral non-linearity ? 12-bit modes ? <12-bit modes 1.0 0.5 C2.7 to +1.9 C0.7 to +0.5 lsb 4 5 e fs full-scale error ? 12-bit modes ? <12-bit modes C4 C1.4 C5.4 C1.8 lsb 4 v adin = v dda 5 e q quantization error ? 16-bit modes ? 13-bit modes C1 to 0 0.5 lsb 4 enob effective number of bits 16-bit differential mode ? avg = 32 ? avg = 4 16-bit single-ended mode ? avg = 32 ? avg = 4 12.8 11.9 12.2 11.4 14.5 13.8 13.9 13.1 bits bits bits bits 6 sinad signal-to-noise plus distortion see enob 6.02 enob + 1.76 db thd total harmonic distortion 16-bit differential mode ? avg = 32 16-bit single-ended mode ? avg = 32 -94 -85 db db 7 sfdr spurious free dynamic range 16-bit differential mode ? avg = 32 16-bit single-ended mode 82 78 95 90 db db 7 table continues on the next page... peripheral operating requirements and behaviors kinetis k22f 512kb flash, rev. 7.1, 08/2016 41 nxp semiconductors table 30. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) (continued) symbol description conditions 1 min. typ. 2 max. unit notes ? avg = 32 e il input leakage error i in r as mv i in = leakage current (refer to the mcu's voltage and current operating ratings) temp sensor slope across the full temperature range of the device 1.55 1.62 1.69 mv/c 8 v temp25 temp sensor voltage 25 c 706 716 726 mv 8 1. all accuracy numbers assume the adc is calibrated with v refh = v dda 2. typical values assume v dda = 3.0 v, temp = 25 c, f adck = 2.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 3. the adc supply current depends on the adc conversion clock speed, conversion rate and adc_cfg1[adlpc] (low power). for lowest power operation, adc_cfg1[adlpc] must be set, the adc_cfg2[adhsc] bit must be clear with 1 mhz adc conversion clock speed. 4. 1 lsb = (v refh - v refl )/2 n 5. adc conversion clock < 16 mhz, max hardware averaging (avge = %1, avgs = %11) 6. input data is 100 hz sine wave. adc conversion clock < 12 mhz. 7. input data is 1 khz sine wave. adc conversion clock < 12 mhz. 8. adc conversion clock < 3 mhz typical adc 16-bit differential enob vs adc clock 100hz, 90% fs sine input enob adc clock frequency (mhz) 15.00 14.70 14.40 14.10 13.80 13.50 13.20 12.90 12.60 12.30 12.00 1 2 3 4 5 6 7 8 9 10 1211 hardware averaging disabled averaging of 4 samples averaging of 8 samples averaging of 32 samples figure 15. typical enob vs. adc_clk for 16-bit differential mode peripheral operating requirements and behaviors 42 kinetis k22f 512kb flash, rev. 7.1, 08/2016 nxp semiconductors typical adc 16-bit single-ended enob vs adc clock 100hz, 90% fs sine input enob adc clock frequency (mhz) 14.00 13.75 13.25 13.00 12.75 12.50 12.00 11.75 11.50 11.25 11.00 1 2 3 4 5 6 7 8 9 10 1211 averaging of 4 samples averaging of 32 samples 13.50 12.25 figure 16. typical enob vs. adc_clk for 16-bit single-ended mode 3.6.2 cmp and 6-bit dac electrical specifications table 31. comparator and 6-bit dac electrical specifications symbol description min. typ. max. unit v dd supply voltage 1.71 3.6 v i ddhs supply current, high-speed mode (en=1, pmode=1) 200 a i ddls supply current, low-speed mode (en=1, pmode=0) 20 a v ain analog input voltage v ss C 0.3 v dd v v aio analog input offset voltage 20 mv v h analog comparator hysteresis 1 ? cr0[hystctr] = 00 ? cr0[hystctr] = 01 ? cr0[hystctr] = 10 ? cr0[hystctr] = 11 5 10 20 30 mv mv mv mv v cmpoh output high v dd C 0.5 v v cmpol output low 0.5 v t dhs propagation delay, high-speed mode (en=1, pmode=1) 20 50 200 ns t dls propagation delay, low-speed mode (en=1, pmode=0) 80 250 600 ns analog comparator initialization delay 2 40 s i dac6b 6-bit dac current adder (enabled) 7 a inl 6-bit dac integral non-linearity C0.5 0.5 lsb 3 dnl 6-bit dac differential non-linearity C0.3 0.3 lsb peripheral operating requirements and behaviors kinetis k22f 512kb flash, rev. 7.1, 08/2016 43 nxp semiconductors 1. typical hysteresis is measured with input voltage range limited to 0.6 to v dd C0.6 v. 2. comparator initialization delay is defined as the time between software writes to change control inputs (writes to cmp_daccr[dacen], cmp_daccr[vrsel], cmp_daccr[vosel], cmp_muxcr[psel], and cmp_muxcr[msel]) and the comparator output settling to a stable level. 3. 1 lsb = v reference /64 00 01 10 hystctr setting 0.1 10 11 vin level (v) cmp hystereris (v) 3.1 2.82.5 2.2 1.91.61.3 1 0.70.4 0.05 0 0.01 0.02 0.03 0.08 0.07 0.06 0.04 figure 17. typical hysteresis vs. vin level (vdd = 3.3 v, pmode = 0) peripheral operating requirements and behaviors 44 kinetis k22f 512kb flash, rev. 7.1, 08/2016 nxp semiconductors 00 01 10 hystctr setting 10 11 0.1 3.12.82.5 2.2 1.91.61.3 1 0.70.4 0.1 0 0.02 0.04 0.06 0.18 0.14 0.12 0.08 0.16 vin level (v) cmp hysteresis (v) figure 18. typical hysteresis vs. vin level (vdd = 3.3 v, pmode = 1) 3.6.3 12-bit dac electrical characteristics 3.6.3.1 12-bit dac operating requirements table 32. 12-bit dac operating requirements symbol desciption min. max. unit notes v dda supply voltage 1.71 3.6 v v dacr reference voltage 1.13 3.6 v 1 c l output load capacitance 100 pf 2 i l output load current 1 ma 1. the dac reference can be selected to be v dda or v refh . 2. a small load capacitance (47 pf) can improve the bandwidth performance of the dac. peripheral operating requirements and behaviors kinetis k22f 512kb flash, rev. 7.1, 08/2016 45 nxp semiconductors 3.6.3.2 12-bit dac operating behaviors table 33. 12-bit dac operating behaviors symbol description min. typ. max. unit notes i dda_dacl p supply current low-power mode 330 a i dda_dach p supply current high-speed mode 1200 a t daclp full-scale settling time (0x080 to 0xf7f) low-power mode 100 200 s 1 t dachp full-scale settling time (0x080 to 0xf7f) high-power mode 15 30 s 1 t ccdaclp code-to-code settling time (0xbf8 to 0xc08) low-power mode and high-speed mode 0.7 1 s 1 v dacoutl dac output voltage range low high- speed mode, no load, dac set to 0x000 100 mv v dacouth dac output voltage range high high- speed mode, no load, dac set to 0xfff v dacr ?100 v dacr mv inl integral non-linearity error high speed mode 8 lsb 2 dnl differential non-linearity error v dacr > 2 v 1 lsb 3 dnl differential non-linearity error v dacr = vref_out 1 lsb 4 v offset offset error 0.4 0.8 %fsr 5 e g gain error 0.1 0.6 %fsr 5 psrr power supply rejection ratio, v dda 2.4 v 60 90 db t co temperature coefficient offset voltage 3.7 v/c 6 t ge temperature coefficient gain error 0.000421 %fsr/c rop output resistance (load = 3 k) 250 sr slew rate -80h f7fh 80h ? high power (sp hp ) ? low power (sp lp ) 1.2 0.05 1.7 0.12 v/s bw 3db bandwidth ? high power (sp hp ) ? low power (sp lp ) 550 40 khz 1. settling within 1 lsb 2. the inl is measured for 0 + 100 mv to v dacr ?100 mv 3. the dnl is measured for 0 + 100 mv to v dacr ?100 mv 4. the dnl is measured for 0 + 100 mv to v dacr ?100 mv with v dda > 2.4 v 5. calculated by a best fit curve from v ss + 100 mv to v dacr ? 100 mv 6. v dda = 3.0 v, reference select set for v dda (dacx_co:dacrfs = 1), high power mode (dacx_c0:lpen = 0), dac set to 0x800, temperature range is across the full range of the device peripheral operating requirements and behaviors 46 kinetis k22f 512kb flash, rev. 7.1, 08/2016 nxp semiconductors digital code dac12 inl (lsb) 0 500 1000 1500 2000 2500 3000 3500 4000 2 4 6 8 -2 -4 -6 -8 0 figure 19. typical inl error vs. digital code peripheral operating requirements and behaviors kinetis k22f 512kb flash, rev. 7.1, 08/2016 47 nxp semiconductors temperature c dac12 mid level code voltage 25 55 85 105 125 1.499 -40 1.4985 1.498 1.4975 1.497 1.4965 1.496 figure 20. offset at half scale vs. temperature 3.6.4 voltage reference electrical specifications table 34. vref full-range operating requirements symbol description min. max. unit notes v dda supply voltage 1.71 3.6 v t a temperature operating temperature range of the device c c l output load capacitance 100 nf 1 , 2 1. c l must be connected to vref_out if the vref_out functionality is being used for either an internal or external reference. 2. the load capacitance should not exceed +/-25% of the nominal specified c l value over the operating temperature range of the device. peripheral operating requirements and behaviors 48 kinetis k22f 512kb flash, rev. 7.1, 08/2016 nxp semiconductors table 35. vref full-range operating behaviors symbol description min. typ. max. unit notes v out voltage reference output with factory trim at nominal v dda and temperature=25c 1.1920 1.1950 1.1980 v 1 v out voltage reference output with user trim at nominal v dda and temperature=25c 1.1945 1.1950 1.1955 v 1 v step voltage reference trim step 0.5 mv 1 v tdrift temperature drift (vmax -vmin across the full temperature range) 15 mv 1 i bg bandgap only current 80 a i lp low-power buffer current 360 ua 1 i hp high-power buffer current 1 ma 1 v load load regulation ? current = 1.0 ma 200 v 1 , 2 t stup buffer startup time 100 s t chop_osc_st up internal bandgap start-up delay with chop oscillator enabled 35 ms v vdrift voltage drift (vmax -vmin across the full voltage range) 2 mv 1 1. see the chip's reference manual for the appropriate settings of the vref status and control register. 2. load regulation voltage is the difference between the vref_out voltage with no load vs. voltage with defined load table 36. vref limited-range operating requirements symbol description min. max. unit notes t a temperature 0 70 c table 37. vref limited-range operating behaviors symbol description min. max. unit notes v tdrift temperature drift (v max -v min across the limited temperature range) 10 mv 3.7 timers see general switching specifications . 3.8 communication interfaces peripheral operating requirements and behaviors kinetis k22f 512kb flash, rev. 7.1, 08/2016 49 nxp semiconductors 3.8.1 usb electrical specifications the usb electricals for the usb on-the-go module conform to the standards documented by the universal serial bus implementers forum. for the most up-to-date standards, visit usb.org . note the mcgpllclk meets the usb jitter and signaling rate specifications for certification with the use of an external clock/crystal for both device and host modes. the mcgfllclk does not meet the usb jitter or signaling rate specifications for certification. the irc48m meets the usb jitter and signaling rate specifications for certification in device mode when the usb clock recovery mode is enabled. it does not meet the usb signaling rate specifications for certification in host mode operation. 3.8.2 usb vreg electrical specifications table 38. usb vreg electrical specifications symbol description min. typ. 1 max. unit notes vregin input supply voltage 2.7 5.5 v i ddon quiescent current run mode, load current equal zero, input supply (vregin) > 3.6 v 125 186 a i ddstby quiescent current standby mode, load current equal zero 1.1 10 a i ddoff quiescent current shutdown mode ? vregin = 5.0 v and temperature=25 c ? across operating voltage and temperature 650 4 na a i loadrun maximum load current run mode 120 ma i loadstby maximum load current standby mode 1 ma v reg33out regulator output voltage input supply (vregin) > 3.6 v ? run mode ? standby mode 3 2.1 3.3 2.8 3.6 3.6 v v table continues on the next page... peripheral operating requirements and behaviors 50 kinetis k22f 512kb flash, rev. 7.1, 08/2016 nxp semiconductors table 38. usb vreg electrical specifications (continued) symbol description min. typ. 1 max. unit notes v reg33out regulator output voltage input supply (vregin) < 3.6 v, pass-through mode 2.1 3.6 v 2 c out external output capacitor 1.76 2.2 8.16 f esr external output capacitor equivalent series resistance 1 100 m i lim short circuit current 290 ma 1. typical values assume vregin = 5.0 v, temp = 25 c unless otherwise stated. 2. operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to i load . 3.8.3 dspi switching specifications (limited voltage range) the deserial serial peripheral interface (dspi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the tables below provide dspi timing characteristics for classic spi timing modes. refer to the spi chapter of the reference manual for information on the modified transfer formats used for communicating with slower peripheral devices. table 39. master mode dspi timing (limited voltage range) num description min. max. unit notes operating voltage 2.7 3.6 v frequency of operation 30 mhz ds1 dspi_sck output cycle time 2 x t bus ns ds2 dspi_sck output high/low time (t sck /2) ? 2 (t sck /2) + 2 ns ds3 dspi_pcs n valid to dspi_sck delay (t bus x 2) ? 2 ns 1 ds4 dspi_sck to dspi_pcs n invalid delay (t bus x 2) ? 2 ns 2 ds5 dspi_sck to dspi_sout valid 8.5 ns ds6 dspi_sck to dspi_sout invalid -2 ns ds7 dspi_sin to dspi_sck input setup 16.2 ns ds8 dspi_sck to dspi_sin input hold 0 ns 1. the delay is programmable in spix_ctarn[pssck] and spix_ctarn[cssck]. 2. the delay is programmable in spix_ctarn[pasc] and spix_ctarn[asc]. peripheral operating requirements and behaviors kinetis k22f 512kb flash, rev. 7.1, 08/2016 51 nxp semiconductors ds3 ds4 ds1 ds2 ds7 ds8 first data last data ds5 first data data last data ds6 data dspi_pcsn dspi_sck (cpol=0) dspi_sin dspi_sout figure 21. dspi classic spi timing master mode table 40. slave mode dspi timing (limited voltage range) num description min. max. unit notes operating voltage 2.7 3.6 v frequency of operation 15 mhz 1 ds9 dspi_sck input cycle time 4 x t bus ns ds10 dspi_sck input high/low time (t sck /2) ? 2 (t sck /2) + 2 ns ds11 dspi_sck to dspi_sout valid 21.4 ns ds12 dspi_sck to dspi_sout invalid 0 ns ds13 dspi_sin to dspi_sck input setup 2.6 ns ds14 dspi_sck to dspi_sin input hold 7 ns ds15 dspi_ss active to dspi_sout driven 17 ns ds16 dspi_ss inactive to dspi_sout not driven 17 ns 1. the maximum operating frequency is measured with noncontinuous cs and sck. when dspi is configured with continuous cs and sck, the spi clock must not be greater than 1/6 of the bus clock. for example, when the bus clock is 60 mhz, the spi clock must not be greater than 10 mhz. first data last data first data data last data data ds15 ds10 ds9 ds16 ds11 ds12 ds14 ds13 dspi_ss dspi_sck (cpol=0) dspi_sout dspi_sin figure 22. dspi classic spi timing slave mode peripheral operating requirements and behaviors 52 kinetis k22f 512kb flash, rev. 7.1, 08/2016 nxp semiconductors 3.8.4 dspi switching specifications (full voltage range) the deserial serial peripheral interface (dspi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the tables below provides dspi timing characteristics for classic spi timing modes. refer to the spi chapter of the reference manual for information on the modified transfer formats used for communicating with slower peripheral devices. table 41. master mode dspi timing (full voltage range) num description min. max. unit notes operating voltage 1.71 3.6 v 1 frequency of operation 15 mhz ds1 dspi_sck output cycle time 4 x t bus ns ds2 dspi_sck output high/low time (t sck /2) - 4 (t sck/2) + 4 ns ds3 dspi_pcs n valid to dspi_sck delay (t bus x 2) ? 4 ns 2 ds4 dspi_sck to dspi_pcs n invalid delay (t bus x 2) ? 4 ns 3 ds5 dspi_sck to dspi_sout valid 10 ns ds6 dspi_sck to dspi_sout invalid -4.5 ns ds7 dspi_sin to dspi_sck input setup 24.6 ns ds8 dspi_sck to dspi_sin input hold 0 ns 1. the dspi module can operate across the entire operating voltage for the processor, but to run across the full voltage range the maximum frequency of operation is reduced. 2. the delay is programmable in spix_ctarn[pssck] and spix_ctarn[cssck]. 3. the delay is programmable in spix_ctarn[pasc] and spix_ctarn[asc]. ds3 ds4 ds1 ds2 ds7 ds8 first data last data ds5 first data data last data ds6 data dspi_pcsn dspi_sck (cpol=0) dspi_sin dspi_sout figure 23. dspi classic spi timing master mode peripheral operating requirements and behaviors kinetis k22f 512kb flash, rev. 7.1, 08/2016 53 nxp semiconductors table 42. slave mode dspi timing (full voltage range) num description min. max. unit operating voltage 1.71 3.6 v frequency of operation 7.5 mhz ds9 dspi_sck input cycle time 8 x t bus ns ds10 dspi_sck input high/low time (t sck /2) - 4 (t sck/2) + 4 ns ds11 dspi_sck to dspi_sout valid 29.5 ns ds12 dspi_sck to dspi_sout invalid 0 ns ds13 dspi_sin to dspi_sck input setup 3.2 ns ds14 dspi_sck to dspi_sin input hold 7 ns ds15 dspi_ss active to dspi_sout driven 25 ns ds16 dspi_ss inactive to dspi_sout not driven 25 ns first data last data first data data last data data ds15 ds10 ds9 ds16 ds11 ds12 ds14 ds13 dspi_ss dspi_sck (cpol=0) dspi_sout dspi_sin figure 24. dspi classic spi timing slave mode 3.8.5 inter-integrated circuit interface (i 2 c) timing table 43. i 2 c timing characteristic symbol standard mode fast mode unit minimum maximum minimum maximum scl clock frequency f scl 0 100 0 400 1 khz hold time (repeated) start condition. after this period, the first clock pulse is generated. t hd ; sta 4 0.6 s low period of the scl clock t low 4.7 1.25 s high period of the scl clock t high 4 0.6 s set-up time for a repeated start condition t su ; sta 4.7 0.6 s table continues on the next page... peripheral operating requirements and behaviors 54 kinetis k22f 512kb flash, rev. 7.1, 08/2016 nxp semiconductors table 43. i 2 c timing (continued) characteristic symbol standard mode fast mode unit minimum maximum minimum maximum data hold time for i 2 c bus devices t hd ; dat 0 2 3.45 3 0 4 0.9 2 s data set-up time t su ; dat 250 5 100 3 , 6 ns rise time of sda and scl signals t r 1000 20 +0.1c b 7 300 ns fall time of sda and scl signals t f 300 20 +0.1c b 6 300 ns set-up time for stop condition t su ; sto 4 0.6 s bus free time between stop and start condition t buf 4.7 1.3 s pulse width of spikes that must be suppressed by the input filter t sp n/a n/a 0 50 ns 1. the maximum scl clock frequency in fast mode with maximum bus loading can only be achieved when using the high drive pins across the full voltage range and when using the normal drive pins and vdd 2.7 v. 2. the master mode i 2 c deasserts ack of an address byte simultaneously with the falling edge of scl. if no slaves acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the sda and scl lines. 3. the maximum thd; dat must be met only if the device does not stretch the low period (tlow) of the scl signal. 4. input signal slew = 10 ns and output load = 50 pf 5. set-up time in slave-transmitter mode is 1 ipbus clock period, if the tx fifo is empty. 6. a fast mode i 2 c bus device can be used in a standard mode i2c bus system, but the requirement t su; dat 250 ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, then it must output the next data bit to the sda line t rmax + t su; dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification) before the scl line is released. 7. c b = total capacitance of the one bus line in pf. table 44. i 2 c 1 mbps timing characteristic symbol minimum maximum unit scl clock frequency f scl 0 1 1 mhz hold time (repeated) start condition. after this period, the first clock pulse is generated. t hd ; sta 0.26 s low period of the scl clock t low 0.5 s high period of the scl clock t high 0.26 s set-up time for a repeated start condition t su ; sta 0.26 s data hold time for i 2 c bus devices t hd ; dat 0 s data set-up time t su ; dat 50 ns rise time of sda and scl signals t r 20 +0.1c b , 2 120 ns fall time of sda and scl signals t f 20 +0.1c b 2 120 ns set-up time for stop condition t su ; sto 0.26 s bus free time between stop and start condition t buf 0.5 s pulse width of spikes that must be suppressed by the input filter t sp 0 50 ns peripheral operating requirements and behaviors kinetis k22f 512kb flash, rev. 7.1, 08/2016 55 nxp semiconductors 1. the maximum scl clock frequency of 1 mbps can support maximum bus loading when using the high drive pins across the full voltage range. 2. c b = total capacitance of the one bus line in pf. ? ? sda hd; sta t hd; dat t low t su; dat t high t su; sta sr p s s t hd; sta t sp t su; sto t buf t f t r t f t r scl figure 25. timing definition for devices on the i 2 c bus 3.8.6 uart switching specifications see general switching specifications . 3.8.7 i2s/sai switching specifications this section provides the ac timing for the i2s/sai module in master mode (clocks are driven) and slave mode (clocks are input). all timing is given for noninverted serial clock polarity (tcr2[bcp] is 0, rcr2[bcp] is 0) and a noninverted frame sync (tcr4[fsp] is 0, rcr4[fsp] is 0). if the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the bit clock signal (bclk) and/or the frame sync (fs) signal shown in the following figures. 3.8.7.1 normal run, wait and stop mode performance over a limited operating voltage range this section provides the operating performance over a limited operating voltage for the device in normal run, wait and stop modes. table 45. i2s/sai master mode timing in normal run, wait and stop modes (limited voltage range) num. characteristic min. max. unit operating voltage 2.7 3.6 v s1 i2s_mclk cycle time 40 ns s2 i2s_mclk pulse width high/low 45% 55% mclk period table continues on the next page... peripheral operating requirements and behaviors 56 kinetis k22f 512kb flash, rev. 7.1, 08/2016 nxp semiconductors table 45. i2s/sai master mode timing in normal run, wait and stop modes (limited voltage range) (continued) num. characteristic min. max. unit s3 i2s_tx_bclk/i2s_rx_bclk cycle time (output) 80 ns s4 i2s_tx_bclk/i2s_rx_bclk pulse width high/low 45% 55% bclk period s5 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output valid 15 ns s6 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output invalid 0 ns s7 i2s_tx_bclk to i2s_txd valid 15 ns s8 i2s_tx_bclk to i2s_txd invalid 0 ns s9 i2s_rxd/i2s_rx_fs input setup before i2s_rx_bclk 18 ns s10 i2s_rxd/i2s_rx_fs input hold after i2s_rx_bclk 0 ns s1 s2 s2 s3 s4 s4 s5 s9 s7 s9 s10 s7 s8 s6 s10 s8 i2s_mclk (output) i2s_tx_bclk/ i2s_rx_bclk (output) i2s_tx_fs/ i2s_rx_fs (output) i2s_tx_fs/ i2s_rx_fs (input) i2s_txd i2s_rxd figure 26. i2s/sai timing master modes table 46. i2s/sai slave mode timing in normal run, wait and stop modes (limited voltage range) num. characteristic min. max. unit operating voltage 2.7 3.6 v s11 i2s_tx_bclk/i2s_rx_bclk cycle time (input) 80 ns s12 i2s_tx_bclk/i2s_rx_bclk pulse width high/low (input) 45% 55% mclk period s13 i2s_tx_fs/i2s_rx_fs input setup before i2s_tx_bclk/i2s_rx_bclk 4.5 ns table continues on the next page... peripheral operating requirements and behaviors kinetis k22f 512kb flash, rev. 7.1, 08/2016 57 nxp semiconductors table 46. i2s/sai slave mode timing in normal run, wait and stop modes (limited voltage range) (continued) num. characteristic min. max. unit s14 i2s_tx_fs/i2s_rx_fs input hold after i2s_tx_bclk/i2s_rx_bclk 2 ns s15 i2s_tx_bclk to i2s_txd/i2s_tx_fs output valid 20 ns s16 i2s_tx_bclk to i2s_txd/i2s_tx_fs output invalid 0 ns s17 i2s_rxd setup before i2s_rx_bclk 4.5 ns s18 i2s_rxd hold after i2s_rx_bclk 2 ns s19 i2s_tx_fs input assertion to i2s_txd output valid 1 25 ns 1. applies to first bit in each frame and only if the tcr4[fse] bit is clear s15 s13 s15 s17 s18 s15 s16 s16 s14 s16 s11 s12 s12 i2s_tx_bclk/ i2s_rx_bclk (input) i2s_tx_fs/ i2s_rx_fs (output) i2s_txd i2s_rxd i2s_tx_fs/ i2s_rx_fs (input) s19 figure 27. i2s/sai timing slave modes 3.8.7.2 normal run, wait and stop mode performance over the full operating voltage range this section provides the operating performance over the full operating voltage for the device in normal run, wait and stop modes. table 47. i2s/sai master mode timing in normal run, wait and stop modes (full voltage range) num. characteristic min. max. unit operating voltage 1.71 3.6 v s1 i2s_mclk cycle time 40 ns s2 i2s_mclk pulse width high/low 45% 55% mclk period table continues on the next page... peripheral operating requirements and behaviors 58 kinetis k22f 512kb flash, rev. 7.1, 08/2016 nxp semiconductors table 47. i2s/sai master mode timing in normal run, wait and stop modes (full voltage range) (continued) num. characteristic min. max. unit s3 i2s_tx_bclk/i2s_rx_bclk cycle time (output) 80 ns s4 i2s_tx_bclk/i2s_rx_bclk pulse width high/low 45% 55% bclk period s5 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output valid 15 ns s6 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output invalid -1.0 ns s7 i2s_tx_bclk to i2s_txd valid 15 ns s8 i2s_tx_bclk to i2s_txd invalid 0 ns s9 i2s_rxd/i2s_rx_fs input setup before i2s_rx_bclk 27 ns s10 i2s_rxd/i2s_rx_fs input hold after i2s_rx_bclk 0 ns s1 s2 s2 s3 s4 s4 s5 s9 s7 s9 s10 s7 s8 s6 s10 s8 i2s_mclk (output) i2s_tx_bclk/ i2s_rx_bclk (output) i2s_tx_fs/ i2s_rx_fs (output) i2s_tx_fs/ i2s_rx_fs (input) i2s_txd i2s_rxd figure 28. i2s/sai timing master modes table 48. i2s/sai slave mode timing in normal run, wait and stop modes (full voltage range) num. characteristic min. max. unit operating voltage 1.71 3.6 v s11 i2s_tx_bclk/i2s_rx_bclk cycle time (input) 80 ns s12 i2s_tx_bclk/i2s_rx_bclk pulse width high/low (input) 45% 55% mclk period s13 i2s_tx_fs/i2s_rx_fs input setup before i2s_tx_bclk/i2s_rx_bclk 5.8 ns table continues on the next page... peripheral operating requirements and behaviors kinetis k22f 512kb flash, rev. 7.1, 08/2016 59 nxp semiconductors table 48. i2s/sai slave mode timing in normal run, wait and stop modes (full voltage range) (continued) num. characteristic min. max. unit s14 i2s_tx_fs/i2s_rx_fs input hold after i2s_tx_bclk/i2s_rx_bclk 2 ns s15 i2s_tx_bclk to i2s_txd/i2s_tx_fs output valid 28.5 ns s16 i2s_tx_bclk to i2s_txd/i2s_tx_fs output invalid 0 ns s17 i2s_rxd setup before i2s_rx_bclk 5.8 ns s18 i2s_rxd hold after i2s_rx_bclk 2 ns s19 i2s_tx_fs input assertion to i2s_txd output valid 1 26.3 ns 1. applies to first bit in each frame and only if the tcr4[fse] bit is clear s15 s13 s15 s17 s18 s15 s16 s16 s14 s16 s11 s12 s12 i2s_tx_bclk/ i2s_rx_bclk (input) i2s_tx_fs/ i2s_rx_fs (output) i2s_txd i2s_rxd i2s_tx_fs/ i2s_rx_fs (input) s19 figure 29. i2s/sai timing slave modes 3.8.7.3 vlpr, vlpw, and vlps mode performance over the full operating voltage range this section provides the operating performance over the full operating voltage for the device in vlpr, vlpw, and vlps modes. table 49. i2s/sai master mode timing in vlpr, vlpw, and vlps modes (full voltage range) num. characteristic min. max. unit operating voltage 1.71 3.6 v s1 i2s_mclk cycle time 62.5 ns s2 i2s_mclk pulse width high/low 45% 55% mclk period s3 i2s_tx_bclk/i2s_rx_bclk cycle time (output) 250 ns table continues on the next page... peripheral operating requirements and behaviors 60 kinetis k22f 512kb flash, rev. 7.1, 08/2016 nxp semiconductors table 49. i2s/sai master mode timing in vlpr, vlpw, and vlps modes (full voltage range) (continued) num. characteristic min. max. unit s4 i2s_tx_bclk/i2s_rx_bclk pulse width high/low 45% 55% bclk period s5 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output valid 45 ns s6 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output invalid -1 ns s7 i2s_tx_bclk to i2s_txd valid 45 ns s8 i2s_tx_bclk to i2s_txd invalid 0 ns s9 i2s_rxd/i2s_rx_fs input setup before i2s_rx_bclk 45 ns s10 i2s_rxd/i2s_rx_fs input hold after i2s_rx_bclk 0 ns s1 s2 s2 s3 s4 s4 s5 s9 s7 s9 s10 s7 s8 s6 s10 s8 i2s_mclk (output) i2s_tx_bclk/ i2s_rx_bclk (output) i2s_tx_fs/ i2s_rx_fs (output) i2s_tx_fs/ i2s_rx_fs (input) i2s_txd i2s_rxd figure 30. i2s/sai timing master modes table 50. i2s/sai slave mode timing in vlpr, vlpw, and vlps modes (full voltage range) num. characteristic min. max. unit operating voltage 1.71 3.6 v s11 i2s_tx_bclk/i2s_rx_bclk cycle time (input) 250 ns s12 i2s_tx_bclk/i2s_rx_bclk pulse width high/low (input) 45% 55% mclk period s13 i2s_tx_fs/i2s_rx_fs input setup before i2s_tx_bclk/i2s_rx_bclk 30 ns s14 i2s_tx_fs/i2s_rx_fs input hold after i2s_tx_bclk/i2s_rx_bclk 7 ns s15 i2s_tx_bclk to i2s_txd/i2s_tx_fs output valid 63 ns table continues on the next page... peripheral operating requirements and behaviors kinetis k22f 512kb flash, rev. 7.1, 08/2016 61 nxp semiconductors table 50. i2s/sai slave mode timing in vlpr, vlpw, and vlps modes (full voltage range) (continued) num. characteristic min. max. unit s16 i2s_tx_bclk to i2s_txd/i2s_tx_fs output invalid 0 ns s17 i2s_rxd setup before i2s_rx_bclk 30 ns s18 i2s_rxd hold after i2s_rx_bclk 4 ns s19 i2s_tx_fs input assertion to i2s_txd output valid 1 72 ns 1. applies to first bit in each frame and only if the tcr4[fse] bit is clear s15 s13 s15 s17 s18 s15 s16 s16 s14 s16 s11 s12 s12 i2s_tx_bclk/ i2s_rx_bclk (input) i2s_tx_fs/ i2s_rx_fs (output) i2s_txd i2s_rxd i2s_tx_fs/ i2s_rx_fs (input) s19 figure 31. i2s/sai timing slave modes 4 dimensions 4.1 obtaining package dimensions package dimensions are provided in package drawings. to find a package drawing, go to nxp.com and perform a keyword search for the drawings document number: if you want the drawing for this package then use this document number 64-pin lqfp 98ass23234w 64-pin mapbga 98asa00420d 88-pin qfn 98asa00935d table continues on the next page... dimensions 62 kinetis k22f 512kb flash, rev. 7.1, 08/2016 nxp semiconductors if you want the drawing for this package then use this document number 100-pin lqfp 98ass23308w 121-pin xfbga 98asa00595d 5 pinout 5.1 k22f signal multiplexing and pin assignments the following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. the port control module is responsible for selecting which alt functionality is available on each pin. note the mk22fn512vfx12 (88qfn) does not support the flexbus function. 64 map bga 64 lqfp 88 qfn 100 lqfp 121 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport a1 1 1 1 e4 pte0/ clkout3 2k adc1_ se4a adc1_ se4a pte0/ clkout3 2k spi1_ pcs1 uart1_ tx i2c1_sda rtc_ clkout b1 2 2 2 e3 pte1/ llwu_p0 adc1_ se5a adc1_ se5a pte1/ llwu_p0 spi1_ sout uart1_ rx i2c1_scl spi1_sin 3 3 e2 pte2/ llwu_p1 adc1_ se6a adc1_ se6a pte2/ llwu_p1 spi1_sck uart1_ cts_b 4 4 f4 pte3 adc1_ se7a adc1_ se7a pte3 spi1_sin uart1_ rts_b spi1_ sout 5 5 h7 pte4/ llwu_p2 disabled pte4/ llwu_p2 spi1_ pcs0 lpuart0 _tx 6 6 g4 pte5 disabled pte5 spi1_ pcs2 lpuart0 _rx ftm3_ ch0 7 7 f3 pte6 disabled pte6 spi1_ pcs3 lpuart0 _cts_b i2s0_ mclk ftm3_ ch1 usb_ sof_out c5 3 8 8 e6 vdd vdd vdd c4 4 9 9 g7 vss vss vss 9 l6 vss vss vss e1 5 10 10 f1 usb0_dp usb0_dp usb0_dp d1 6 11 11 f2 usb0_dm usb0_dm usb0_dm e2 7 12 12 g1 vout33 vout33 vout33 d2 8 13 13 g2 vregin vregin vregin pinout kinetis k22f 512kb flash, rev. 7.1, 08/2016 63 nxp semiconductors 64 map bga 64 lqfp 88 qfn 100 lqfp 121 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 14 h1 adc0_ dp1 adc0_ dp1 adc0_ dp1 15 h2 adc0_ dm1 adc0_ dm1 adc0_ dm1 14 16 j1 adc1_ dp1/ adc0_ dp2 adc1_ dp1/ adc0_ dp2 adc1_ dp1/ adc0_ dp2 15 17 j2 adc1_ dm1/ adc0_ dm2 adc1_ dm1/ adc0_ dm2 adc1_ dm1/ adc0_ dm2 g1 9 16 18 k1 adc0_ dp0/ adc1_ dp3 adc0_ dp0/ adc1_ dp3 adc0_ dp0/ adc1_ dp3 f1 10 17 19 k2 adc0_ dm0/ adc1_ dm3 adc0_ dm0/ adc1_ dm3 adc0_ dm0/ adc1_ dm3 g2 11 20 l1 adc1_ dp0/ adc0_ dp3 adc1_ dp0/ adc0_ dp3 adc1_ dp0/ adc0_ dp3 f2 12 21 l2 adc1_ dm0/ adc0_ dm3 adc1_ dm0/ adc0_ dm3 adc1_ dm0/ adc0_ dm3 f4 13 18 22 f5 vdda vdda vdda g4 14 19 23 g5 vrefh vrefh vrefh g3 15 20 24 g6 vrefl vrefl vrefl f3 16 21 25 f6 vssa vssa vssa j3 adc1_ se16/ adc0_ se22 adc1_ se16/ adc0_ se22 adc1_ se16/ adc0_ se22 h3 adc0_ se16/ cmp1_ in2/ adc0_ se21 adc0_ se16/ cmp1_ in2/ adc0_ se21 adc0_ se16/ cmp1_ in2/ adc0_ se21 h1 17 22 26 l3 vref_ out/ cmp1_ in5/ cmp0_ in5/ vref_ out/ cmp1_ in5/ cmp0_ in5/ vref_ out/ cmp1_ in5/ cmp0_ in5/ pinout 64 kinetis k22f 512kb flash, rev. 7.1, 08/2016 nxp semiconductors 64 map bga 64 lqfp 88 qfn 100 lqfp 121 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport adc1_ se18 adc1_ se18 adc1_ se18 h2 18 23 27 k5 dac0_ out/ cmp1_ in3/ adc0_ se23 dac0_ out/ cmp1_ in3/ adc0_ se23 dac0_ out/ cmp1_ in3/ adc0_ se23 k4 dac1_ out/ cmp0_ in4/ adc1_ se23 dac1_ out/ cmp0_ in4/ adc1_ se23 dac1_ out/ cmp0_ in4/ adc1_ se23 l7 rtc_ wakeup_ b rtc_ wakeup_ b rtc_ wakeup_ b h3 19 24 28 l4 xtal32 xtal32 xtal32 h4 20 25 29 l5 extal32 extal32 extal32 h5 21 26 30 k6 vbat vbat vbat 31 h5 pte24 adc0_ se17 adc0_ se17 pte24 i2c0_scl ewm_ out_b 32 j5 pte25 adc0_ se18 adc0_ se18 pte25 i2c0_sda ewm_in 33 h6 pte26/ clkout3 2k disabled pte26/ clkout3 2k rtc_ clkout usb_ clkin d3 22 27 34 j6 pta0 jtag_ tclk/ swd_ clk/ ezp_clk pta0 uart0_ cts_b ftm0_ ch5 jtag_ tclk/ swd_clk ezp_clk d4 23 28 35 h8 pta1 jtag_ tdi/ ezp_di pta1 uart0_ rx ftm0_ ch6 jtag_tdi ezp_di e5 24 29 36 j7 pta2 jtag_ tdo/ trace_ swo/ ezp_do pta2 uart0_ tx ftm0_ ch7 jtag_ tdo/ trace_ swo ezp_do d5 25 30 37 h9 pta3 jtag_ tms/ swd_dio pta3 uart0_ rts_b ftm0_ ch0 jtag_ tms/ swd_dio g5 26 31 38 j8 pta4/ llwu_p3 nmi_b/ ezp_cs_ b pta4/ llwu_p3 ftm0_ ch1 nmi_b ezp_cs_ b f5 27 32 39 k7 pta5 disabled pta5 usb_ clkin ftm0_ ch2 i2s0_tx_ bclk jtag_ trst_b pinout kinetis k22f 512kb flash, rev. 7.1, 08/2016 65 nxp semiconductors 64 map bga 64 lqfp 88 qfn 100 lqfp 121 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 33 40 e5 vdd vdd vdd 34 41 g3 vss vss vss j9 pta10 disabled pta10 ftm2_ ch0 ftm2_ qd_pha j4 pta11 disabled pta11 ftm2_ ch1 ftm2_ qd_phb h6 28 35 42 k8 pta12 disabled pta12 ftm1_ ch0 i2s0_ txd0 ftm1_ qd_pha g6 29 36 43 l8 pta13/ llwu_p4 disabled pta13/ llwu_p4 ftm1_ ch1 i2s0_tx_ fs ftm1_ qd_phb 37 44 k9 pta14 disabled pta14 spi0_ pcs0 uart0_ tx i2s0_rx_ bclk 38 45 l9 pta15 disabled pta15 spi0_sck uart0_ rx i2s0_ rxd0 39 46 j10 pta16 disabled pta16 spi0_ sout uart0_ cts_b i2s0_rx_ fs 40 47 h10 pta17 adc1_ se17 adc1_ se17 pta17 spi0_sin uart0_ rts_b i2s0_ mclk g7 30 41 48 l10 vdd vdd vdd h7 31 42 49 k10 vss vss vss h8 32 43 50 l11 pta18 extal0 extal0 pta18 ftm0_ flt2 ftm_ clkin0 g8 33 44 51 k11 pta19 xtal0 xtal0 pta19 ftm1_ flt0 ftm_ clkin1 lptmr0_ alt1 f8 34 45 52 j11 reset_b reset_b reset_b h11 pta29 disabled pta29 fb_a24 f7 35 46 53 g11 ptb0/ llwu_p5 adc0_ se8/ adc1_ se8 adc0_ se8/ adc1_ se8 ptb0/ llwu_p5 i2c0_scl ftm1_ ch0 ftm1_ qd_pha f6 36 47 54 g10 ptb1 adc0_ se9/ adc1_ se9 adc0_ se9/ adc1_ se9 ptb1 i2c0_sda ftm1_ ch1 ftm1_ qd_phb e7 37 48 55 g9 ptb2 adc0_ se12 adc0_ se12 ptb2 i2c0_scl uart0_ rts_b ftm0_ flt3 e8 38 49 56 g8 ptb3 adc0_ se13 adc0_ se13 ptb3 i2c0_sda uart0_ cts_b ftm0_ flt0 50 f11 ptb6 adc1_ se12 adc1_ se12 ptb6 fb_ad23 51 e11 ptb7 adc1_ se13 adc1_ se13 ptb7 fb_ad22 52 d11 ptb8 disabled ptb8 lpuart0 _rts_b fb_ad21 pinout 66 kinetis k22f 512kb flash, rev. 7.1, 08/2016 nxp semiconductors 64 map bga 64 lqfp 88 qfn 100 lqfp 121 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 53 57 e10 ptb9 disabled ptb9 spi1_ pcs1 lpuart0 _cts_b fb_ad20 54 58 d10 ptb10 adc1_ se14 adc1_ se14 ptb10 spi1_ pcs0 lpuart0 _rx fb_ad19 ftm0_ flt1 55 59 c10 ptb11 adc1_ se15 adc1_ se15 ptb11 spi1_sck lpuart0 _tx fb_ad18 ftm0_ flt2 60 vss vss vss 61 vdd vdd vdd e6 39 56 62 b10 ptb16 disabled ptb16 spi1_ sout uart0_ rx ftm_ clkin0 fb_ad17 ewm_in d7 40 57 63 e9 ptb17 disabled ptb17 spi1_sin uart0_ tx ftm_ clkin1 fb_ad16 ewm_ out_b d6 41 58 64 d9 ptb18 disabled ptb18 ftm2_ ch0 i2s0_tx_ bclk fb_ad15 ftm2_ qd_pha c7 42 59 65 c9 ptb19 disabled ptb19 ftm2_ ch1 i2s0_tx_ fs fb_oe_b ftm2_ qd_phb 66 f10 ptb20 disabled ptb20 fb_ad31 cmp0_ out 67 f9 ptb21 disabled ptb21 fb_ad30 cmp1_ out 68 f8 ptb22 disabled ptb22 fb_ad29 69 e8 ptb23 disabled ptb23 spi0_ pcs5 fb_ad28 d8 43 60 70 b9 ptc0 adc0_ se14 adc0_ se14 ptc0 spi0_ pcs4 pdb0_ extrg usb_ sof_out fb_ad14 c6 44 61 71 d8 ptc1/ llwu_p6 adc0_ se15 adc0_ se15 ptc1/ llwu_p6 spi0_ pcs3 uart1_ rts_b ftm0_ ch0 fb_ad13 i2s0_ txd0 lpuart0 _rts_b b7 45 62 72 c8 ptc2 adc0_ se4b/ cmp1_in0 adc0_ se4b/ cmp1_in0 ptc2 spi0_ pcs2 uart1_ cts_b ftm0_ ch1 fb_ad12 i2s0_tx_ fs lpuart0 _cts_b c8 46 63 73 b8 ptc3/ llwu_p7 cmp1_in1 cmp1_in1 ptc3/ llwu_p7 spi0_ pcs1 uart1_ rx ftm0_ ch2 clkout i2s0_tx_ bclk lpuart0 _rx e3 47 64 74 vss vss vss e4 48 65 75 vdd vdd vdd b8 49 66 76 a8 ptc4/ llwu_p8 disabled ptc4/ llwu_p8 spi0_ pcs0 uart1_ tx ftm0_ ch3 fb_ad11 cmp1_ out lpuart0 _tx a8 50 67 77 d7 ptc5/ llwu_p9 disabled ptc5/ llwu_p9 spi0_sck lptmr0_ alt2 i2s0_ rxd0 fb_ad10 cmp0_ out ftm0_ ch2 a7 51 68 78 c7 ptc6/ llwu_ p10 cmp0_in0 cmp0_in0 ptc6/ llwu_ p10 spi0_ sout pdb0_ extrg i2s0_rx_ bclk fb_ad9 i2s0_ mclk b6 52 69 79 b7 ptc7 cmp0_in1 cmp0_in1 ptc7 spi0_sin usb_ sof_out i2s0_rx_ fs fb_ad8 pinout kinetis k22f 512kb flash, rev. 7.1, 08/2016 67 nxp semiconductors 64 map bga 64 lqfp 88 qfn 100 lqfp 121 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport a6 53 70 80 a7 ptc8 adc1_ se4b/ cmp0_in2 adc1_ se4b/ cmp0_in2 ptc8 ftm3_ ch4 i2s0_ mclk fb_ad7 b5 54 81 d6 ptc9 adc1_ se5b/ cmp0_in3 adc1_ se5b/ cmp0_in3 ptc9 ftm3_ ch5 i2s0_rx_ bclk fb_ad6 ftm2_ flt0 b4 55 82 c6 ptc10 adc1_ se6b adc1_ se6b ptc10 i2c1_scl ftm3_ ch6 i2s0_rx_ fs fb_ad5 a5 56 83 c5 ptc11/ llwu_ p11 adc1_ se7b adc1_ se7b ptc11/ llwu_ p11 i2c1_sda ftm3_ ch7 fb_rw_b 71 84 b6 ptc12 disabled ptc12 fb_ad27 ftm3_ flt0 72 85 a6 ptc13 disabled ptc13 fb_ad26 73 86 a5 ptc14 disabled ptc14 fb_ad25 74 87 b5 ptc15 disabled ptc15 fb_ad24 88 vss vss vss 89 vdd vdd vdd 75 90 d5 ptc16 disabled ptc16 lpuart0 _rx fb_cs5_ b/ fb_tsiz1/ fb_be23_ 16_ bls15_8_ b 76 91 c4 ptc17 disabled ptc17 lpuart0 _tx fb_cs4_ b/ fb_tsiz0/ fb_be31_ 24_bls7_ 0_b 77 92 b4 ptc18 disabled ptc18 lpuart0 _rts_b fb_tbst_ b/ fb_cs2_ b/ fb_be15_ 8_bls23_ 16_b 78 a4 ptc19 disabled ptc19 lpuart0 _cts_b fb_cs3_ b/ fb_be7_ 0_bls31_ 24_b fb_ta_b c3 57 79 93 d4 ptd0/ llwu_ p12 disabled ptd0/ llwu_ p12 spi0_ pcs0 uart2_ rts_b ftm3_ ch0 fb_ale/ fb_cs1_ b/ fb_ts_b lpuart0 _rts_b pinout 68 kinetis k22f 512kb flash, rev. 7.1, 08/2016 nxp semiconductors 64 map bga 64 lqfp 88 qfn 100 lqfp 121 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport a4 58 80 94 d3 ptd1 adc0_ se5b adc0_ se5b ptd1 spi0_sck uart2_ cts_b ftm3_ ch1 fb_cs0_b lpuart0 _cts_b c2 59 81 95 c3 ptd2/ llwu_ p13 disabled ptd2/ llwu_ p13 spi0_ sout uart2_ rx ftm3_ ch2 fb_ad4 lpuart0 _rx i2c0_scl b3 60 82 96 b3 ptd3 disabled ptd3 spi0_sin uart2_ tx ftm3_ ch3 fb_ad3 lpuart0 _tx i2c0_sda a3 61 83 97 a3 ptd4/ llwu_ p14 disabled ptd4/ llwu_ p14 spi0_ pcs1 uart0_ rts_b ftm0_ ch4 fb_ad2 ewm_in spi1_ pcs0 c1 62 84 98 a2 ptd5 adc0_ se6b adc0_ se6b ptd5 spi0_ pcs2 uart0_ cts_b ftm0_ ch5 fb_ad1 ewm_ out_b spi1_sck 85 f7 vss vss vss 86 e7 vdd vdd vdd b2 63 87 99 b2 ptd6/ llwu_ p15 adc0_ se7b adc0_ se7b ptd6/ llwu_ p15 spi0_ pcs3 uart0_ rx ftm0_ ch6 fb_ad0 ftm0_ flt0 spi1_ sout a2 64 88 100 a1 ptd7 disabled ptd7 uart0_ tx ftm0_ ch7 ftm0_ flt1 spi1_sin a10 ptd8 disabled ptd8 i2c0_scl lpuart0 _rx fb_a16 a9 ptd9 disabled ptd9 i2c0_sda lpuart0 _tx fb_a17 b1 ptd10 disabled ptd10 lpuart0 _rts_b fb_a18 c2 ptd11 disabled ptd11 lpuart0 _cts_b fb_a19 c1 ptd12 disabled ptd12 ftm3_ flt0 fb_a20 d2 ptd13 disabled ptd13 fb_a21 d1 ptd14 disabled ptd14 fb_a22 e1 ptd15 disabled ptd15 fb_a23 a11 nc nc nc k3 nc nc nc h4 nc nc nc b11 nc nc nc c11 nc nc nc 5.2 recommended connection for unused analog and digital pins the following table shows the recommended connections for analog interface pins if those analog interfaces are not used in the customer's application. pinout kinetis k22f 512kb flash, rev. 7.1, 08/2016 69 nxp semiconductors table 51. recommended connection for unused analog interfaces pin type short recommendation detailed recommendation analog/non gpio pgax/adcx float analog input - float analog/non gpio adcx/cmpx float analog input - float analog/non gpio vref_out float analog output - float analog/non gpio dacx_out float analog output - float analog/non gpio rtc_wakeup_b float analog output - float analog/non gpio xtal32 float analog output - float analog/non gpio extal32 float analog input - float gpio/analog pta18/extal0 float analog input - float gpio/analog pta19/xtal0 float analog output - float gpio/analog ptx/adcx float float (default is analog input) gpio/analog ptx/cmpx float float (default is analog input) gpio/digital pta0/jtag_tclk float float (default is jtag with pulldown) gpio/digital pta1/jtag_tdi float float (default is jtag with pullup) gpio/digital pta2/jtag_tdo float float (default is jtag with pullup) gpio/digital pta3/jtag_tms float float (default is jtag with pullup) gpio/digital pta4/nmi_b 10k? pullup or disable and float pull high or disable in pcr & fopt and float gpio/digital ptx float float (default is disabled) usb usb0_dp float float usb usb0_dm float float usb vout33 tie to input and ground through 10k? tie to input and ground through 10k? usb vregin tie to output and ground through 10k? tie to output and ground through 10k? vbat vbat float float vdda vdda always connect to vdd potential always connect to vdd potential vrefh vrefh always connect to vdd potential always connect to vdd potential vrefl vrefl always connect to vss potential always connect to vss potential vssa vssa always connect to vss potential always connect to vss potential pinout 70 kinetis k22f 512kb flash, rev. 7.1, 08/2016 nxp semiconductors 5.3 k22 pinouts the following figure shows the pinout diagram for the devices supported by this document. many signals may be multiplexed onto a single pin. to determine what signals can be used on which pin, see the previous section. extal32 xtal32 dac0_out/cmp1_in3/adc0_se23 vref_out/cmp1_in5/cmp0_in5/adc1_se18 vssa vrefl vrefh vdda adc1_dm0/adc0_dm3 adc1_dp0/adc0_dp3 adc0_dm0/adc1_dm3 adc0_dp0/adc1_dp3 vregin vout33 usb0_dm usb0_dp vss vdd pte1/llwu_p0 pte0/clkout32k 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 64 63 62 61 ptd7 ptd6/llwu_p15 ptd5 ptd4/llwu_p14 ptd3 ptd2/llwu_p13 ptd1 ptd0/llwu_p12 ptc11/llwu_p11 ptc10 ptc9 ptc8 ptc7 ptc6/llwu_p10 ptc5/llwu_p9 ptc4/llwu_p8 vdd vss ptc3/llwu_p7 ptc2 ptc1/llwu_p6 ptc0 ptb19 ptb18 ptb17 ptb16 ptb3 ptb2 ptb1 ptb0/llwu_p5 reset_b pta19 pta18 vss vdd pta13/llwu_p4 pta12 pta5 pta4/llwu_p3 pta3 pta2 pta1 pta0 vbat figure 32. k22f 64 lqfp pinout diagram (top view) pinout kinetis k22f 512kb flash, rev. 7.1, 08/2016 71 nxp semiconductors 1 a pte0/ clkout32k b pte1/ llwu_p0 c ptd5 d usb0_dm e usb0_dp f adc0_dm0/ adc1_dm3 g adc0_dp0/ adc1_dp3 1 h vref_out/ cmp1_in5/ cmp0_in5/ adc1_se18 2 ptd7 ptd6/ llwu_p15 ptd2/ llwu_p13 vregin vout33 adc1_dm0/ adc0_dm3 adc1_dp0/ adc0_dp3 2 dac0_out/ cmp1_in3/ adc0_se23 3 ptd4/ llwu_p14 ptd3 ptd0/ llwu_p12 pta0 vss vssa vrefl 3 xtal32 4 ptd1 ptc10 vss pta1 vdd vdda vrefh 4 extal32 5 ptc11/ llwu_p11 ptc9 vdd pta3 pta2 pta5 pta4/ llwu_p3 5 vbat 6 ptc8 ptc7 ptc1/ llwu_p6 ptb18 ptb16 ptb1 pta13/ llwu_p4 6 pta12 7 ptc6/ llwu_p10 ptc2 ptb19 ptb17 ptb2 ptb0/ llwu_p5 vdd 7 vss 8 a ptc5/ llwu_p9 b ptc4/ llwu_p8 c ptc3/ llwu_p7 d ptc0 e ptb3 f reset_b g pta19 8 h pta18 figure 33. k22f 64 mapbga pinout diagram (transparent top view) pinout 72 kinetis k22f 512kb flash, rev. 7.1, 08/2016 nxp semiconductors 1 pte0/clkout32k 2 pte1/llwu_p0 3 pte2/llwu_p1 4 pte3 5 pte4/llwu_p2 6 pte5 7 pte6 8 vdd 9 vss vss 10 usb0_dp 11 usb0_dm 12 vout33 13 vregin 14 adc1_dp1/adc0_dp2 15 adc1_dm1/adc0_dm2 16 adc0_dp0/adc1_dp3 17 adc0_dm0/adc1_dm3 18 vdda 19 vrefh 20 vrefl 21 vssa 22 vref_out/cmp1_in5/cmp0_in5/adc1_se18 23 dac0_out/cmp1_in3/adc0_se23 24 xtal32 25 extal32 26 vbat 27 pta0 28 pta1 29 pta2 30 pta3 31 pta4/llwu_p3 32 pta5 33 vdd 34 vss 35 pta12 36 pta13/llwu_p4 37 pta14 38 pta15 39 pta16 40 pta17 41 vdd 42 vss 43 pta18 44 pta19 45 reset_b 46 ptb0/llwu_p5 47 ptb1 48 ptb2 49 ptb3 50 ptb6 51 ptb7 52 ptb8 53 ptb9 54 ptb10 55 ptb11 56 ptb16 57 ptb17 58 ptb18 59 ptb19 60 ptc0 61 ptc1/llwu_p6 62 ptc2 63 ptc3/llwu_p7 64 vss 65 vdd 66 ptc4/llwu_p8 67 ptc5/llwu_p9 68 ptc6/llwu_p10 69 ptc7 70 ptc8 71 ptc12 72 ptc13 73 ptc14 74 ptc15 75 ptc16 76 ptc17 77 ptc18 78 ptc19 79 ptd0/llwu_p12 80 ptd1 81 ptd2/llwu_p13 82 ptd3 83 ptd4/llwu_p14 84 ptd5 85 vss 86 vdd 87 ptd6/llwu_p15 88 ptd7 figure 34. k22f 88 qfn pinout diagram (transparent top view) note for more information about qfn package use, see electrical connection recommendations for the exposed pad on qfn and dfn packages . pinout kinetis k22f 512kb flash, rev. 7.1, 08/2016 73 nxp semiconductors 60 59 58 57 56 55 54 53 52 51 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 adc1_dp0/adc0_dp3 adc0_dm0/adc1_dm3 adc0_dp0/adc1_dp3 adc1_dm1/adc0_dm2 adc1_dp1/adc0_dp2 adc0_dm1 adc0_dp1 vregin vout33 usb0_dm usb0_dp vss vdd pte6 pte5 pte4/llwu_p2 pte3 pte2/llwu_p1 pte1/llwu_p0 pte0/clkout32k 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 vdd vss ptc3/llwu_p7 ptc2 ptc1/llwu_p6 ptc0 ptb23 ptb22 ptb21 ptb20 ptb19 ptb18 ptb17 ptb16 vdd vss ptb11 ptb10 ptb9 ptb3 ptb2 ptb1 ptb0/llwu_p5 reset_b pta19 25 24 23 22 21 vssa vrefl vrefh vdda adc1_dm0/adc0_dm3 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 99 79 78 77 76 ptd6/llwu_p15 ptc7 ptc6/llwu_p10 ptc5/llwu_p9 ptc4/llwu_p8 50 49 48 47 46 45 44 43 42 41 pta18 vss vdd pta17 pta16 pta15 pta14 pta13/llwu_p4 pta12 vss vdd pta5 pta4/llwu_p3 pta3 pta2 pta1 pta0 pte26/clkout32k pte25 pte24 vbat extal32 xtal32 dac0_out/cmp1_in3/adc0_se23 vref_out/cmp1_in5/cmp0_in5/adc1_se18 98 ptd5 97 ptd4/llwu_p14 96 ptd3 95 ptd2/llwu_p13 94 ptd1 93 ptd0/llwu_p12 92 ptc18 91 ptc17 90 ptc16 89 vdd 88 vss 80 ptc8 ptc9 ptc10 81 82 83 ptc11/llwu_p11 84 ptc12 85 ptc13 86 ptc14 87 ptc15 100 ptd7 figure 35. k22f 100 lqfp pinout diagram (top view) pinout 74 kinetis k22f 512kb flash, rev. 7.1, 08/2016 nxp semiconductors 1 a ptd7 b ptd10 c ptd12 d ptd14 e ptd15 f usb0_dp g vout33 h adc0_dp1 j adc1_dp1/ adc0_dp2 k adc0_dp0/ adc1_dp3 1 l adc1_dp0/ adc0_dp3 2 ptd5 ptd6/ llwu_p15 ptd11 ptd13 pte2/ llwu_p1 usb0_dm vregin adc0_dm1 adc1_dm1/ adc0_dm2 adc0_dm0/ adc1_dm3 2 adc1_dm0/ adc0_dm3 3 ptd4/ llwu_p14 ptd3 ptd2/ llwu_p13 ptd1 pte1/ llwu_p0 pte6 vss adc0_se16/ cmp1_in2/ adc0_se21 adc1_se16/ adc0_se22 nc 3 vref_out/ cmp1_in5/ cmp0_in5/ adc1_se18 4 ptc19 ptc18 ptc17 ptd0/ llwu_p12 pte0/ clkout32k pte3 pte5 nc pta11 dac1_out/ cmp0_in4/ adc1_se23 4 xtal32 5 ptc14 ptc15 ptc11/ llwu_p11 ptc16 vdd vdda vrefh pte24 pte25 dac0_out/ cmp1_in3/ adc0_se23 5 extal32 6 ptc13 ptc12 ptc10 ptc9 vdd vssa vrefl pte26/ clkout32k pta0 vbat 6 vss 7 ptc8 ptc7 ptc6/ llwu_p10 ptc5/ llwu_p9 vdd vss vss pte4/ llwu_p2 pta2 pta5 7 rtc_ wakeup_b 8 ptc4/ llwu_p8 ptc3/ llwu_p7 ptc2 ptc1/ llwu_p6 ptb23 ptb22 ptb3 pta1 pta4/ llwu_p3 pta12 8 pta13/ llwu_p4 9 ptd9 ptc0 ptb19 ptb18 ptb17 ptb21 ptb2 pta3 pta10 pta14 9 pta15 10 ptd8 ptb16 ptb11 ptb10 ptb9 ptb20 ptb1 pta17 pta16 vss 10 vdd 11 a nc b nc c nc d ptb8 e ptb7 f ptb6 g ptb0/ llwu_p5 h pta29 j reset_b k pta19 11 l pta18 figure 36. k22f 121 xfbga pinout diagram (transparent top view) 6 part identification 6.1 description part numbers for the chip have fields that identify the specific part. you can use the values of these fields to determine the specific part you have received. part identification kinetis k22f 512kb flash, rev. 7.1, 08/2016 75 nxp semiconductors 6.2 format part numbers for this device have the following format: q k## a m fff r t pp cc n 6.3 fields this table lists the possible values for each field in the part number (not all combinations are valid): field description values q qualification status ? m = fully qualified, general market flow, full reel ? p = prequalification ? k = fully qualified, general market flow, 100 piece reel k## kinetis family ? k22 a key attribute ? d = cortex-m4 w/ dsp ? f = cortex-m4 w/ dsp and fpu m flash memory type ? n = program flash only ? x = program flash and flexmemory fff program flash memory size ? 128 = 128 kb ? 256 = 256 kb ? 512 = 512 kb r silicon revision ? z = initial ? (blank) = main ? a = revision after main t temperature range (c) ? v = C40 to 105 ? c = C40 to 85 pp package identifier ? lh = 64 lqfp (10 mm x 10 mm) ? mp = 64 mapbga (5 mm x 5 mm) ? fx = 88 qfn (10mm x 10mm) ? ll = 100 lqfp (14 mm x 14 mm) ? mc = 121 xfbga (8 mm x 8 mm) ? dc = 121 xfbga (8 mm x 8 mm x 0.5 mm) cc maximum cpu frequency (mhz) ? 5 = 50 mhz ? 7 = 72 mhz ? 10 = 100 mhz ? 12 = 120 mhz ? 15 = 150 mhz n packaging type ? r = tape and reel part identification 76 kinetis k22f 512kb flash, rev. 7.1, 08/2016 nxp semiconductors 6.4 example this is an example part number: MK22FN512VDC12 6.5 121-pin xfbga part marking the 121-pin xfbga package parts follow the part-marking scheme in the following table. table 52. 121-pin xfbga part marking mk partnumber mk part marking MK22FN512VDC12 m22j9vdc 6.6 64-pin mapbga part marking the 64-pin mapbga package parts follow the part-marking scheme in the following table. table 53. 64-pin mapbga part marking mk partnumber mk part marking mk22fn512vmp12 m22j9v 7 terminology and guidelines 7.1 definitions key terms are defined in the following table: term definition rating a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: ? operating ratings apply during operation of the chip. ? handling ratings apply when the chip is not powered. table continues on the next page... terminology and guidelines kinetis k22f 512kb flash, rev. 7.1, 08/2016 77 nxp semiconductors term definition note: the likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. operating requirement a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip operating behavior a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions typical value a specified value for a technical characteristic that: ? lies within the range of values specified by the operating behavior ? is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions note: typical values are provided as design guidelines and are neither tested nor guaranteed. 7.2 examples operating rating : operating requirement : operating behavior that includes a typical value : example example example example 7.3 typical-value conditions typical values assume you meet the following conditions (or other conditions as specified): terminology and guidelines 78 kinetis k22f 512kb flash, rev. 7.1, 08/2016 nxp semiconductors symbol description value unit t a ambient temperature 25 c v dd supply voltage 3.3 v 7.4 relationship between ratings and operating requirements C - no permanent failure - correct operation normal operating range fatal range expected permanent failure fatal range expected permanent failure operating rating (max.) operating requirement (max.) operating requirement (min.) operating rating (min.) operating (power on) degraded operating range degraded operating range C no permanent failure handling range fatal range expected permanent failure fatal range expected permanent failure handling rating (max.) handling rating (min.) handling (power off) - no permanent failure - possible decreased life - possible incorrect operation - no permanent failure - possible decreased life - possible incorrect operation 7.5 guidelines for ratings and operating requirements follow these guidelines for ratings and operating requirements: ? never exceed any of the chips ratings. ? during normal operation, dont exceed any of the chips operating requirements. ? if you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 8 revision history the following table provides a revision history for this document. revision history kinetis k22f 512kb flash, rev. 7.1, 08/2016 79 nxp semiconductors table 54. revision history rev. no. date substantial changes 7.1 08/2016 ? removed the footnote "information related to the 88 qfn package is preliminary" in front matter ? added engineering bulletin in related resource table ? updated the front matter by adding footnotes ? added terminology and guidelines section ? added device revision number table ? updated chip errata naming convention in related resource table 7 11/2015 ? added information related 88 qfn package 6 10/2015 ? in "power consumption operating behaviors" section, added "low power mode peripheral adderstypical value" table ? in "thermal operating requirements" table, in footnote, corrected "t j = t a + ja " to "t j = t a + r ja " ? updated "irc48m specifications" table ? updated "nvm program/erase timing specifications" table; removed row for t hversall and added row for t hversblk256k ? updated "flash command timing specifications" table; added rows for t rd1blk256k and t ersblk256k ? in "slave mode dspi timing (limited voltage range)" table, added footnote regarding maximum frequency of operation ? added new section, "recommended connections for unused analog and digital pins" 5 4/2015 ? on page 1: ? added the certified usb-if logo ? in first bullet of introduction, updated power consumption data to align with the data in the "power consumption operating behaviors" table ? in second bullet of introduction, added "usb fs device crystal-less functionality" ? under "security and integrity modules" added "hardware random-number generator" ? under "communication interfaces," updated i 2 c bullet to indicate support for up to 1 mbps operation ? under "operating characteristics," specified that voltage range includes flash writes ? in figure, "functional block diagram," added "random-number generator." ? in "voltage and current operating requirements" table: ? removed content related to positive injection ? updated footnote 1 to say that all analog and i/o pins are internally clamped to v ss only (not v ss and v dd )through esd protection diodes. ? in"power consumption operating behaviors" table: ? added additional temperature data in power consumption table ? added max idd values based on characterization results equivalent to mean + 3 sigma ? updated "emc radiated emissions operating behaviors" table ? in "thermal operating requirements" table, added the following footnote for ambient temperature: "maximum t a can be exceeded only if the user ensures that t j does not exceed maximum t j . the simplest method to determine t j is: t j = t a + ja x chip power dissipation" ? updated "irc48m specifications": ? updated maximum values for firc48m_ol_lv and firc48m_ol_hv (full temperature) ? added specifications for firc48m_ol_hv (-40c to 85c) ? updated notes in "usb electrical specifications" section ? in "i 2 c timing" table, table continues on the next page... revision history 80 kinetis k22f 512kb flash, rev. 7.1, 08/2016 nxp semiconductors table 54. revision history (continued) rev. no. date substantial changes ? added the following footnote on maximum fast mode value for scl clock frequency: "the maximum scl clock frequency in fast mode with maximum bus loading can only be achieved when using the high drive pins across the full voltage range and when using the normal drive pins and vdd 2.7 v." ? updated minimum fast mode value for low period of the scl clock to 1.25 ? added "i 2 c 1 mbps timing" table ? removed section 6, "ordering parts." ? specified that the figure, "k22f 64 lqfp pinout diagram" is a top view ? specified that the figure, "k22f 64 mapbga pinout diagram" is a transparent top view ? specified that the figure, "k22f 100 lqfp pinout diagram" is a top view ? corrected part marking shown in "64-pin mapbga part marking" table 4 7/2014 ? in "power consumption operating behaviors table": ? updated existing typical power measurements ? added new typical power measurements for the following: ? idd_hsrun (high speed run mode current executing coremark code) ? idd_runco (run mode current in compute operation, executing coremark code) ? idd_run (run mode current in compute operation, executing while(1) loop) ? idd_vlpr (very low power mode current executing coremark code) ? idd_vlpr (very low power run mode current in compute operation, executing while(1) loop) ? in "thermal attributes" table, added values for 64 mapbga package 3 5/2014 ? in "voltage and current operating ratings" table, updated maximum digital supply current ? updated "voltage and current operating behaviors" table ? updated "power mode transition operating behaviors" table ? updated "power consumption operating behaviors" table ? updated "emc radiated emissions operating behaviors for 64 lqfp package" table ? updated "thermal attributes" table ? updated "mcg specifications" table ? updated "irc48m specifications" table ? updated "16-bit adc operating conditions" table ? updated "voltage reference electrical specifications" section ? added "64-pin mapbga part marking" table 2 3/2014 initial public release revision history kinetis k22f 512kb flash, rev. 7.1, 08/2016 81 nxp semiconductors how to reach us: home page: nxp.com web support: nxp.com/support information in this document is provided solely to enable system and software implementers to use nxp products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. nxp reserves the right to make changes without further notice to any products herein. nxp makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does nxp assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. typical parameters that may be provided in nxp data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. all operating parameters, including typicals, must be validated for each customer application by customer's technical experts. nxp does not convey any license under its patent rights nor the rights of others. nxp sells products pursuant to standard terms and conditions of sale, which can be found at the following address: nxp.com/salestermsandconditions . nxp, the nxp logo, nxp secure connections for a smarter world, freescale, the freescale logo, and kinetis are trademarks of nxp b.v. all other product or service names are the property of their respective owners. arm, the arm powered logo, and cortex are registered trademarks of arm limited (or its subsidiaries) in the eu and/or elsewhere. the usb-if logo is a registered trademark of usb implementers forum, inc. all rights reserved. ? 2014C2016 nxp b.v. document number k22p121m120sf7 revision 7.1, 08/2016 |
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